[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/ptl: Provide the TCSS port policy setting options

[Jérémy Compostella (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84419?usp=email )

Change subject: soc/intel/ptl: Provide the TCSS port policy setting options
......................................................................

soc/intel/ptl: Provide the TCSS port policy setting options

Each TCSS port can be associated a setting via the tcss_cap_policy
device tree field. The setting can be picked within five values listed
by this commit.

BUG=b/348678529
TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN

Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/include/soc/tcss.h
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84419/1

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 27d766f..85dcccd 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -16,6 +16,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
+#include <soc/tcss.h>
 #include <soc/usb.h>
 #include <stdint.h>

diff --git a/src/soc/intel/pantherlake/include/soc/tcss.h b/src/soc/intel/pantherlake/include/soc/tcss.h
index 79604bc..a1d72b8 100644
--- a/src/soc/intel/pantherlake/include/soc/tcss.h
+++ b/src/soc/intel/pantherlake/include/soc/tcss.h
@@ -16,4 +16,12 @@
 #define BIAS_CTRL_VW_INDEX_SHIFT 24
 #define BIAS_CTRL_BIT_POS_SHIFT 16

+enum {
+	TCSS_TYPE_C_PORT_DISABLE,
+	TCSS_TYPE_C_PORT_DP_ONLY,
+	TCSS_TYPE_C_PORT_NO_TBT,
+	TCSS_TYPE_C_PORT_NO_PCIE,
+	TCSS_TYPE_C_PORT_FULL_FUN = 7
+};
+
 #endif