Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68877 )
Change subject: soc/intel/cmn/block/cse: Clear interrupt status after HECI-1 has been received ......................................................................
soc/intel/cmn/block/cse: Clear interrupt status after HECI-1 has been received
For some server processors, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU.
On a server mainboard, when get_me_fw_version() is called via HECI-1, this change avoids seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Signed-off-by: Jonathan Zhang jonzhang@meta.com
Change-Id: Icdf0ba58d059340b0e53fec822fff6258eeb2622 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c 2 files changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68877/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55a2b49..68cb5d3 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -60,6 +60,12 @@ help Enables CSE Lite SKU
+config SOC_INTEL_CSE_SERVER_SKU + bool + default n + help + Enables CSE Server SKU + config SOC_INTEL_CSE_RW_UPDATE bool "Enable the CSE RW Update Feature" default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2c94ec..e9d830e 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -571,6 +571,8 @@
if ((hdr & MEI_HDR_IS_COMPLETE) && received) { *maxlen = p - (uint8_t *) buff; + if (CONFIG(SOC_INTEL_CSE_SERVER_SKU)) + clear_int(); return CSE_TX_RX_SUCCESS; } }