Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41009 )
Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ......................................................................
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide. Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 27368c0..897f9c4 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -115,7 +115,7 @@ printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
/* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
/* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL,