[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83769?usp=email )

Change subject: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
......................................................................

soc/intel/mtl: enable FSP uGOP config in MTL for eSOL

This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic
ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP
uGOP driver as an underlying technology for rendering eSOL screen.

This patch does not change the binary or the system behaviour.

BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.

Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769
Reviewed-by: Dinesh Gehlot 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 11 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index ec8c318..327b3a2 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -20,6 +20,7 @@
    select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
    select FSP_M_XIP
    select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
+	select FSP_UGOP_EARLY_SIGN_OF_LIFE if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
    select FSP_USES_CB_DEBUG_EVENT_HANDLER
    select FSPS_HAS_ARCH_UPD
    select GENERIC_GPIO_LIB
@@ -457,16 +458,6 @@
    help
      slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Meteor Lake.

-config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE
-	bool
-	default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
-	depends on MAINBOARD_HAS_CHROMEOS
-	select VBT_CBFS_COMPRESSION_DEFAULT_LZ4
-	help
-	  Enable the FSP-M Sign-of-Life feature to display a
-	  configurable text message on screen during memory training
-	  and CSME update.
-
 config SOC_PHYSICAL_ADDRESS_WIDTH
    int
    default 42
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index ec78383..9734c63 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -511,7 +511,7 @@

soc_memory_init_params(m_cfg, config);

-	if (CONFIG(SOC_INTEL_METEORLAKE_SIGN_OF_LIFE))
+	if (CONFIG(CHROMEOS_ENABLE_ESOL))
    	fill_fspm_sign_of_life(m_cfg, arch_upd);

mainboard_memory_init_params(mupd);