build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )
Change subject: Enable long cr50 ready pulses for Tigerlake systems ......................................................................
Patch Set 9:
(6 comments)
https://review.coreboot.org/c/coreboot/+/43741/9/src/drivers/spi/tpm/tpm.c File src/drivers/spi/tpm/tpm.c:
https://review.coreboot.org/c/coreboot/+/43741/9/src/drivers/spi/tpm/tpm.c@3... PS9, Line 354: uint32_t get_cr50_board_cfg() Bad function definition - uint32_t get_cr50_board_cfg() should probably be uint32_t get_cr50_board_cfg(void)
https://review.coreboot.org/c/coreboot/+/43741/9/src/drivers/spi/tpm/tpm.c@6... PS9, Line 638: if (first_access_this_boot()) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/43741/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/chromeos.c:
https://review.coreboot.org/c/coreboot/+/43741/9/src/mainboard/google/voltee... PS9, Line 45: tlcl_lib_init(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/43741/9/src/mainboard/google/voltee... PS9, Line 45: tlcl_lib_init(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/43741/9/src/soc/intel/common/block/... File src/soc/intel/common/block/gspi/gspi.c:
https://review.coreboot.org/c/coreboot/+/43741/9/src/soc/intel/common/block/... PS9, Line 263: memset(gspi_base, 0, sizeof(gspi_base)); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/43741/9/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43741/9/src/soc/intel/tigerlake/fsp... PS9, Line 210: /* S0iX: Selectively enable individual sub-states. code indent should use tabs where possible