Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76017?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for SkipExtGfxScan dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for SkipExtGfxScan dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="SkipExtGfxScan" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: I2058f21c971e054b06eaac86e8547f34f63bb575 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb 6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/76017/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index f487d9c..a505f6a 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,7 @@
# FSP configuration register "SaGv" = "SaGv_Enabled" - register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e77da3b..fe3ad66 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -18,7 +18,7 @@ register "gen3_dec" = "0x00fc0901"
# FSP configuration - register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true register SataSalpSupport = true register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 3f7b503..6b65f34 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -18,7 +18,7 @@ register "gen3_dec" = "0x00fc0901"
# FSP configuration - register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true register SataSalpSupport = true register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0e771eb..93e6b6f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -18,7 +18,7 @@ register SataSalpSupport = true register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" - register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b6318dd..a7769d9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -22,7 +22,7 @@ register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 3a22ed0..f448a20 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -45,7 +45,7 @@ # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS"
- register "SkipExtGfxScan" = "1" + register SkipExtGfxScan = true
register "enable_c6dram" = "1"