[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Correct order of "RUN_FSP_GOP" check

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39313 )

Change subject: soc/intel/tigerlake: Correct order of "RUN_FSP_GOP" check
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39313/3/src/soc/intel/tigerlake/gra... 
File src/soc/intel/tigerlake/graphics.c:

https://review.coreboot.org/c/coreboot/+/39313/3/src/soc/intel/tigerlake/gra... 
PS3, Line 69: 	}
> I am not convinced this is correct. […]

Where does the hang occur? In coreboot? In FSP? Have you debugged what operation is causing that hang? And is this a hard hang? an assert?
> > > When EDP display in not connected we are facing CATERR at "PCI: 00:02.0 init" In coreboot.

We will come up with more data on this CATERR.