10 Jul
2020
10 Jul
'20
8:40 a.m.
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3: -Code-Review
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Gerrit-Change-Number: 42557
Gerrit-PatchSet: 3
Gerrit-Owner: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Fri, 10 Jul 2020 08:40:00 +0000
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