Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8217
-gerrit
commit 41c0b751a810c301e50f73cdf55087e4ae0a2f68 Author: Kane Chen kane.chen@intel.com Date: Thu Jul 17 11:31:57 2014 -0700
rambi: configure USBPHY_COMPBG by the setting in devicetree.cb
USBPHY_COMPBG needs to be configured by project
BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly CQ-DEPEND=CL:208557
Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6 Original-Signed-off-by: Kane Chen kane.chen@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/208731 Original-Reviewed-by: Shawn Nematbakhsh shawnn@chromium.org (cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75 --- src/mainboard/google/rambi/devicetree.cb | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 4f0a016..5914a62 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" register "usb2_per_port_lane3" = "0x00049a09" register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock