[coreboot-gerrit] [S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85600?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
......................................................................

mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)

1. Enable HDA driver
2. Add spkr_tplg = max98360a
3. Add jack_tplg = rt5682

BUG=b:380789023
TEST=emerge-nissa coreboot

Change-Id: I8f78a8641de23eadb03348a31574045702b40554
Signed-off-by: John Su 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85600
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Kapil Porwal 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/uldrenite/Makefile.mk
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
3 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  Kapil Porwal: Looks good to me, approved
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index bc53fdf..aa7e643 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -616,6 +616,7 @@
    select HAVE_PCIE_WWAN
    select HAVE_WWAN_POWER_SEQUENCE
    select DRIVERS_WWAN_FM350GL
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB

config BOARD_GOOGLE_VELL
    select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
index 4c33dad..87f515a 100644
--- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
+++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk
@@ -4,3 +4,5 @@
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 4e6a8b0..38aedaa 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -78,6 +78,13 @@
    # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
    register "tcss_aux_ori" = "0"

+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_audio_link_hda_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
    # Configure external V1P05/Vnn/VnnSx Rails
    register "ext_fivr_settings" = "{
    	.configure_ext_fivr = 1,
@@ -448,5 +455,13 @@
    			device pnp 0c09.0 on end
    		end
    	end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
    end
 end