Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel.
Hello Hung-Te Lin, Nico Huber, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78044?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek: PCI: Fix translation window ......................................................................
soc/mediatek: PCI: Fix translation window
Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail.
Fix translation window by split the MMIO space to multiple tables if its size not a power of 2.
Resolves: https://ticket.coreboot.org/issues/508.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option.
BUS=b:298255933 BRANCH=cherry
Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang jianjun.wang@mediatek.com --- M src/soc/mediatek/common/pcie.c 1 file changed, 56 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/9