[coreboot-gerrit] Change in coreboot[master]: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62722 )

Change subject: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
......................................................................

mb/google/nissa/var/nivviks: Hook up SD host controller GL9750

Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.

BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)

Signed-off-by: Eric Lai 
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) 
Reviewed-by: Kangheui Won 
Reviewed-by: Reka Norman 
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/nivviks/gpio.c
2 files changed, 17 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kangheui Won: Looks good to me, approved
  Reka Norman: Looks good to me, approved

diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 186ca6f..9bf50ae 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -84,6 +84,7 @@
    bool "->  Nivviks"
    select BOARD_GOOGLE_BASEBOARD_NISSA
    select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GENESYSLOGIC_GL9750
    select DRIVERS_INTEL_MIPI_CAMERA
    select HAVE_WWAN_POWER_SEQUENCE

diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c
index f0700ab..a5f9cb8 100644
--- a/src/mainboard/google/brya/variants/nivviks/gpio.c
+++ b/src/mainboard/google/brya/variants/nivviks/gpio.c
@@ -31,6 +31,8 @@

/* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
    /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
    /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
@@ -45,6 +47,13 @@
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
    PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)
@@ -58,3 +67,10 @@
    *num = ARRAY_SIZE(early_gpio_table);
    return early_gpio_table;
 }
+
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}