Attention is currently required from: Alexander Couzens, Angel Pons, Martin L Roth, Nicholas Chin.
Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email )
Change subject: nb/intel/haswell: Move SPD addresses to devicetree ......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79025/comment/a9e91001_3714f705?usp... : PS4, Line 14: Patch also covers recently added Z97 boards using Broadwell MRC.
I had to make a separate follow-up commit for Sandy Bridge because the original refactoring commits […]
Done
File src/northbridge/intel/haswell/broadwell_mrc/raminit.c:
https://review.coreboot.org/c/coreboot/+/79025/comment/433d669a_b6c10cc5?usp... : PS4, Line 377: struct spd_info spdi = {0}; : if (CONFIG(HAVE_SPD_IN_CBFS)) { : /* Obtain the SPD addresses from mainboard code */ : mb_get_spd_map(&spdi); : } else { : /* Boards without memory down: Obtain the SPD addresses from devicetree */ : memcpy(spdi.addresses, cfg->spd_addresses, ARRAY_SIZE(spdi.addresses)); : } :
Yeah, it's to avoid having redundant copies of the source code that may end up out of sync. […]
Done. More aggressive refactoring would be done later, such as the little dance that load and invoke the actual MRC binary, and yes those platform and memory config reporting.