[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/fatcat: Keep GSPIx interface default PCI

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85686?usp=email )

Change subject: mb/google/fatcat: Keep GSPIx interface default PCI
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mb/google/fatcat: Keep GSPIx interface default PCI

BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.

Change-Id: Ia3348f78614e61259333ccf2babf20eaf4666a0e
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85686
Tested-by: build bot (Jenkins) 
Reviewed-by: YH Lin 
---
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  YH Lin: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index f3a0a65..b9dcbbd 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -51,6 +51,12 @@
    	[PchSerialIoIndexUART2] = PchSerialIoDisabled,
    }"

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
+	}"
+
    register "pch_hda_dsp_enable" = "true"
    register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
    register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"