Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58284 )
Change subject: soc/intel/broadwell: Clarify PCIe Non Common Clock mode ......................................................................
soc/intel/broadwell: Clarify PCIe Non Common Clock mode
The "force ASPM" setting actually controls Non Common Clock mode with Spread Spectrum Clocking. Rename the associated variables accordingly and expand the comments according to document 535127 (BDW PCH-LP BS).
Change-Id: I4174f6302d62aea81aa74515e2e3135ee324aa7c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pch/pcie.c 6 files changed, 23 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58284/1
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 39c6554..6e912cd 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -42,8 +42,8 @@ register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1"
- # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" + # Force enable Non Common Clock mode with SSC for PCIe Port1 + register "pcie_port_force_ncc_ssc" = "0x01"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 0570cdc..ffa2d69 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -29,8 +29,8 @@ register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5"
- # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" + # Force enable Non Common Clock mode with SSC for PCIe Port 5 + register "pcie_port_force_ncc_ssc" = "0x10"
# Enable port coalescing register "pcie_port_coalesce" = "1" diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 0a92efe..e623387 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -34,8 +34,8 @@ # Set I2C0 to 1.8V register "sio_i2c0_voltage" = "1"
- # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" + # Force enable Non Common Clock mode with SSC for PCIe Port 3 + register "pcie_port_force_ncc_ssc" = "0x04" register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 08b2c95..a41bf59 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -34,8 +34,8 @@ register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1"
- # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" + # Force enable Non Common Clock mode with SSC for PCIe Port 4 + register "pcie_port_force_ncc_ssc" = "0x10"
# Enable port coalescing register "pcie_port_coalesce" = "1" diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h index 2164a31..6153ffe 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/soc/intel/broadwell/pch/chip.h @@ -49,8 +49,8 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce;
- /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; + /* Force root port Non-Common Clock mode with SSC with port bitmap */ + uint8_t pcie_port_force_ncc_ssc;
/* Put SerialIO devices into ACPI mode instead of a PCI device */ uint8_t sio_acpi_mode; diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 6976c69..43dfe79 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -436,7 +436,7 @@ static void pch_pcie_early(struct device *dev) { const struct soc_intel_broadwell_pch_config *config = config_of(dev); - int do_aspm = 0; + int pcie_ncc_ssc = 0; int rp = root_port_number(dev);
switch (rp) { @@ -448,38 +448,39 @@ * Bits 31:28 of b0d28f0 0x32c register correspond to * Root Ports 4:1. */ - do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); + pcie_ncc_ssc = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: /* * Bit 28 of b0d28f4 0x32c register corresponds to * Root Port 5. */ - do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); + pcie_ncc_ssc = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* * Bit 29 of b0d28f5 0x32c register corresponds to * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); + pcie_ncc_ssc = !!(rpc.b0d28f5_32c & (1 << 29)); break; }
- /* Allow ASPM to be forced on in devicetree */ - if ((config->pcie_port_force_aspm & (1 << (rp - 1)))) - do_aspm = 1; + /* Allow Non Common Clock mode with Spread Spectrum to be forced on in devicetree */ + if (config && (config->pcie_port_force_ncc_ssc & (1 << (rp - 1)))) + pcie_ncc_ssc = 1;
- printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", - rp, do_aspm ? "en" : "dis"); + printk(BIOS_DEBUG, "PCIe Root Port %d Non Common Clock mode with SSC is %sabled\n", + rp, pcie_ncc_ssc ? "en" : "dis");
- if (do_aspm) { - /* Set ASPM bits in MPC2 register. */ + if (pcie_ncc_ssc) { + /* Disable ASPM L0s support in MPC2 register. */ pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
/* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
+ /* Increase the elastic buffer pointer half full pointer values by 2. */ switch (rp) { case 1: pcie_add_0x0202000_iobp(0xe9002440); @@ -522,7 +523,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
/* Set L1 exit latency in LCAP register. */ - if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) + if ((pci_read_config8(dev, 0xf5) & 0x1) || pcie_ncc_ssc) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));