[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8183: update dcxo output buffer setting

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32323 )

Change subject: mediatek/mt8183: update dcxo output buffer setting
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mediatek/mt8183: update dcxo output buffer setting

DCXO consists of core that generates clock and output buffers that
provide clock to other peripheral components.
This patch mainly eliminates the extra power consumption of output buffers.
We only enable the buffer for SOC and disable unused buffers for power-saving.
Also disable useless buffer power mode to guarantee the lowest power state.

BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323
Reviewed-by: Julius Werner 
Reviewed-by: You-Cheng Syu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
2 files changed, 4 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved
  You-Cheng Syu: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 841a202..1f6f06a 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -147,6 +147,7 @@
    PMIC_RG_DCXO_CW15 = 0x07AE,
    PMIC_RG_DCXO_CW16 = 0x07B0,
    PMIC_RG_DCXO_CW21 = 0x07BA,
+	PMIC_RG_DCXO_CW23 = 0x07BE,
    PMIC_RG_DCXO_ELR0 = 0x07C4
 };

diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 5879088..3bd3ab4 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -274,9 +274,10 @@
    rtc_write(PMIC_RG_DCXO_CW16, 0x9855);

/* 26M enable control */
-	/* Enable clock buffer XO_SOC, XO_CEL */
-	rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
+	/* Enable clock buffer XO_SOC */
+	rtc_write(PMIC_RG_DCXO_CW00, 0x4005);
    rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
+	rtc_write(PMIC_RG_DCXO_CW23, 0x0053);

/* Load thermal coefficient */
    rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);