[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45432 )

Change subject: nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
......................................................................

nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}

There's no need to wrap these macros with casts. Removing them allows
dropping `uintptr_t` casts in other files. Changes the binary, though.

Change-Id: I1553cbeee45972d6deba8cb9969c69fceeb19574
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45432
Reviewed-by: HAOUAS Elyes 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/gm45/early_init.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/pcie.c
3 files changed, 5 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 1be3518..e362841 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -9,10 +9,10 @@
    const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);

/* Setup MCHBAR. */
-	pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
+	pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);

/* Setup DMIBAR. */
-	pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
+	pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);

/* Setup EPBAR. */
    pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index dc993cf..6f8d53c 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -170,13 +170,8 @@
 #define CMOS_WRITE_TRAINING	0x90 /* 16 bytes
    				(could be reduced to 10 bytes) */

-#ifndef __ACPI__
-#define DEFAULT_MCHBAR		((u8 *)0xfed14000)
-#define DEFAULT_DMIBAR		((u8 *)0xfed18000)
-#else
 #define DEFAULT_MCHBAR		0xfed14000
 #define DEFAULT_DMIBAR		0xfed18000
-#endif
 #define DEFAULT_EPBAR		0xfed19000
 #define DEFAULT_HECIBAR		((u8 *)0xfed1a000)

@@ -356,6 +351,7 @@
 #define CxDTAEW(x)		(0x1280+(x*0x100))
 #define CxDTC(x)		(0x1288+(x*0x100))

+
 /*
  * DMIBAR
  */
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 5a4999e..0eb1287 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -250,7 +250,7 @@

/* Link1: component ID 1, link valid. */
    EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
-	EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
+	EPBAR32(EPLE1A) = DEFAULT_DMIBAR;

if (peg_enabled)
    	/* Link2: link_valid. */
@@ -268,7 +268,7 @@
    /* Link2: component ID 1 (MCH), link valid */
    DMIBAR32(DMILE2D) =
    	(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
-	DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
+	DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
 }

void gm45_late_init(const stepping_t stepping)