Attention is currently required from: Furquan Shaikh, Aamir Bohra, Patrick Rudolph, Boris Mittelberg. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50599 )
Change subject: soc/intel/alderlake: Fix PCI IRQ tables ......................................................................
Patch Set 5:
(5 comments)
File src/soc/intel/alderlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/50599/comment/574b132b_c0a15d6b PS2, Line 125: CNVI_BT
please remove.
Done
File src/soc/intel/alderlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/50599/comment/62c49890_8c341975 PS4, Line 6: Package(){0x001FFFFF, 0, 0, TRACEHUB_IRQ }, : Package(){0x001FFFFF, 1, 0, HDA_IRQ }, : Package(){0x001FFFFF, 2, 0, SMBUS_IRQ }, : Package(){0x001FFFFF, 3, 0, GBE_IRQ },
I had dumped FSP logs last week and I see that for D31 all functions use INTA which is IRQ#16.
Ack
https://review.coreboot.org/c/coreboot/+/50599/comment/9b02652b_441a4415 PS4, Line 44: CNVI_WIFI_IRQ
D20F3 seems to be configured for INTA which is IRQ#16.
Ack
File src/soc/intel/alderlake/include/soc/irq.h:
https://review.coreboot.org/c/coreboot/+/50599/comment/fc059cca_ad23bf73 PS2, Line 18: #define LPSS_I2C6_IRQ 18 : #define LPSS_I2C7_IRQ 19
can be removed.
Done
https://review.coreboot.org/c/coreboot/+/50599/comment/36a77c37_1790c0ce PS2, Line 57: 24
22
Done