Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )
Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value
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Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9
PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
I think there's more instances of `256` elsewhere?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0
Gerrit-Change-Number: 44498
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Gerrit-Reviewer: Angel Pons
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Gerrit-Comment-Date: Sat, 15 Aug 2020 13:01:01 +0000
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