hakim giydan (hgiydan@marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16554
-gerrit
commit e57083b57879952238ae833cf30143274929ef2c Author: Hakim Giydan hgiydan@marvell.com Date: Thu Sep 8 11:05:53 2016 -0700
soc/marvell/mvmap2315: Add DDR driver
This driver is only a protorype driver, real driver will be integrated at a later time.
Testing: booted successfully.
Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8 Signed-off-by: Hakim Giydan hgiydan@marvell.com --- src/mainboard/google/rotor/Makefile.inc | 1 + src/mainboard/google/rotor/dram_params.c | 245 ++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 6 + src/soc/marvell/mvmap2315/include/soc/sdram.h | 514 +++++++++++++++++++++ src/soc/marvell/mvmap2315/romstage.c | 5 + src/soc/marvell/mvmap2315/sdram.c | 458 ++++++++++++++++++ 6 files changed, 1229 insertions(+)
diff --git a/src/mainboard/google/rotor/Makefile.inc b/src/mainboard/google/rotor/Makefile.inc index e0015e3..f2fa3e1 100644 --- a/src/mainboard/google/rotor/Makefile.inc +++ b/src/mainboard/google/rotor/Makefile.inc @@ -25,4 +25,5 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += memlayout.ld romstage-y += reset.c +romstage-y += dram_params.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/rotor/dram_params.c b/src/mainboard/google/rotor/dram_params.c new file mode 100644 index 0000000..60a417b --- /dev/null +++ b/src/mainboard/google/rotor/dram_params.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/sdram.h> + +struct mvmap2315_sdram_params ddr_params = { + { + 0x1f1f1f1f, + 0x00000100, + 0x00000100, + 0x1f1f1f1f, + 0x00000100, + 0x00000100, + 0x1f1f1f1f, + 0x00000100, + 0x00000100, + 0x1f1f1f1f, + 0x00000100, + 0x00000100, + 0x00010100, + 0x00000100, + 0x00003100, + 0x00010100, + 0x00000100, + 0x00003100, + 0x00010100, + 0x00000100, + 0x00003100, + 0x00010100, + 0x00000100, + 0x00003100, + 0x03230080, + 0x03230081, + 0x03230085, + 0x03230081, + 0x03230080, + 0x03230081, + 0x03230085, + 0x03230081, + 0x03230080, + 0x03230081, + 0x03230085, + 0x03230081, + 0x03230080, + 0x03230081, + 0x03230085, + 0x03230081, + 0x000b0681, + 0x000b0681, + 0x2A1001B8, + 0x2A1001B8, + 0x8000bb04, + 0x8000bb04, + 0x88087700, + 0x88087700, + 0x000b0681, + 0x000b0681, + 0x2A1001B8, + 0x2A1001B8, + 0x8000bb04, + 0x8000bb04, + 0x88087700, + 0x88087700, + 0x000b0681, + 0x000b0681, + 0x2A1001B8, + 0x2A1001B8, + 0x8000bb04, + 0x8000bb04, + 0x88087700, + 0x88087700, + 0x000b0681, + 0x000b0681, + 0x2A1001B8, + 0x2A1001B8, + 0x8000bb04, + 0x8000bb04, + 0x88087700, + 0x88087700, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00bb0000, + 0x00000508, + 0x2A1001B8, + 0x00000508, + 0x00010508, + 0x00010508, + 0x00000508, + 0x2A1001B8, + 0x00000508, + 0x00010508, + 0x00010508, + 0x00000508, + 0x2A1001B8, + 0x00000508, + 0x00010508, + 0x00010508, + 0x00000508, + 0x2A1001B8, + 0x00000508, + 0x00010508, + 0x00010508 + }, + { + 0x04020632, + 0x04020632, + 0x04020632, + 0x04020632, + 0x04020632, + 0x04020632, + 0x04020632, + 0x04020632, + 0x00000010, + 0x00000010, + 0x00000010, + 0x00000010, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00100000, + 0x00000000, + 0x00100001, + 0x00000000, + 0x40100001, + 0x00000000, + 0x80100003, + 0x00000000, + 0xc0100001, + 0x00000001, + 0x00100001, + 0x00000001, + 0x40100001, + 0x00000001, + 0x80100003, + 0x00000001, + 0xc0100001, + 0x221d0c1d, + 0x221d0c1d, + 0x221d0c1d, + 0x221d0c1d, + 0x40601d44, + 0x40601d44, + 0x40601d44, + 0x40601d44, + 0x10001000, + 0x10001000, + 0x10001000, + 0x10001000, + 0x00011000, + 0x00011000, + 0x00011000, + 0x00011000, + 0x0000020a, + 0x0000020a, + 0x0000020a, + 0x0000020a, + 0x0000027e, + 0x0004de19, + 0x0c7600a5, + 0x0000027e, + 0x0004de19, + 0x0c7600a5, + 0x0000027e, + 0x0004de19, + 0x0c7600a5, + 0x0000027e, + 0x0004de19, + 0x0c7600a5, + 0x02020404, + 0x02020404, + 0x02020404, + 0x02020404, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004, + 0x0060003d, + 0x0060003d, + 0x0060003d, + 0x0060003d, + 0x00e000e0, + 0x00e000e0, + 0x00e000e0, + 0x00e000e0, + 0x010c0c08, + 0x010c0c08, + 0x010c0c08, + 0x010c0c08, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000e1c, + 0x00000e1c, + 0x00000e1c, + 0x00000e1c, + 0x0005a200, + 0x000000b0, + 0x000000b0, + 0x000000b0, + 0x000000b0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x16000c00, + 0x16000c00, + 0x16000c00, + 0x16000c00, + 0x00000ff1, + 0xf3000001, + 0xf3020001, + 0xf3020002, + 0xf302000d + }, +}; diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 25bf9d8..c240e0f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -60,4 +60,10 @@ #define MVMAP2315_LCM_BASE 0xE0000000 #define MVMAP2315_LOWPWR_REG 0xE0002000
+#define MVMAP2315_MC_BASE 0xF0020000 +#define MVMAP2315_PHY0_BASE 0xF0034000 +#define MVMAP2315_PHY1_BASE 0xF0035000 +#define MVMAP2315_PHY2_BASE 0xF0036000 +#define MVMAP2315_PHY3_BASE 0xF0037000 + #endif /* __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/sdram.h b/src/soc/marvell/mvmap2315/include/soc/sdram.h index ee87275..3c67ac3 100644 --- a/src/soc/marvell/mvmap2315/include/soc/sdram.h +++ b/src/soc/marvell/mvmap2315/include/soc/sdram.h @@ -17,6 +17,520 @@
#include <stdint.h>
+#include <soc/addressmap.h> +#include <types.h> + +struct mvmap2315_sdram_params { + u32 dphy_params[100]; + u32 mc_params[122]; +}; + +struct mvmap2315_dphy_regs { + u32 dphy_id; + u32 dphy_phy_user0; + u8 reserved0[0x04]; + u32 dphy_flag; + u32 dphy_dq_pad_ctrl0; + u32 dphy_dq_pad_ctrl2; + u8 reserved1[0x08]; + u32 dphy_ck_pad_ctrl0; + u32 dphy_ck_pad_ctrl2; + u8 reserved2[0x04]; + u32 dphy_ck_pad_ctrl6; + u32 dphy_adcm_pad_ctrl0; + u32 dphy_adcm_pad_ctrl2; + u8 reserved3[0x28]; + u32 dphy_dfi_ctrl0; + u32 dphy_dfi_ctrl2; + u32 dphy_dfi_ctrl4; + u32 dphy_dfi_ctrl6; + u32 dphy_wl_ctrl0; + u8 reserved4[0x0c]; + u32 dphy_qsg_ctrl0; + u8 reserved5[0x0c]; + u32 dphy_qsg_d_ctrl0; + u8 reserved6[0x1c]; + u32 dphy_rdlvl_ctrl0; + u8 reserved7[0x0c]; + u32 dphy_cal_pad_ctrl0; + u32 dphy_cal_pad_ctrl2; + u32 dphy_dll_vreg_ctrl; + u32 dphy_vref_ctrl0; + u32 dphy_cat_ctrl0; + u32 dphy_cat_stat0; + u32 dphy_cat_stat2; + u32 dphy_cat_stat4; + u32 dphy_cat_marg0; + u32 dphy_cat_marg2; + u32 dphy_cat_marg4; + u32 dphy_cat_mctl; + u32 dphy_apb_ctrl0; + u32 dphy_monitor; + u32 dphy_adcm_reserve; + u8 reserved8[0x04]; + u32 dphy_dll_ctrl_0; + u8 reserved9[0x1c]; + u32 dphy_dll_ctrl0; + u32 dphy_dll_ctrl2; + u8 reserved10[0x04]; + u32 dphy_dll_tst_out; + u8 reserved11[0x10]; + u32 dphy_dq_dly_ctrl0; + u8 reserved12[0x1c]; + u32 dphy_qs_dly_ctrl0; + u8 reserved13[0x5c]; + u32 dphy_dll_phrng0; + u8 reserved14[0x3c]; + u32 dphy_ca_dly_ctrl0; + u32 dphy_ca_dly_ctrl1; + u32 dphy_ca_dly_ctrl2; + u32 dphy_ca_dly_ctrl3; + u32 dphy_ca_dly_ctrl4; + u8 reserved15[0x0c]; + u32 dphy_ad0_dly_ctrl; + u8 reserved16[0x0c]; + u32 dphy_ck_dly_ctrl0; + u8 reserved17[0x5c]; + u32 dphy_qsg_d_out0; + u8 reserved18[0x12c]; + u32 dphy_lb_ctrl0; + u32 dphy_lb_sts0; + u32 dphy_lb_cnt0; + u8 reserved19[0x04]; + u32 dphy_lb_seed0; + u32 dphy_lb_seed2; +}; + +check_member(mvmap2315_dphy_regs, dphy_lb_seed2, 0x3D4); +static struct mvmap2315_dphy_regs * const mvmap2315_dphy0 + = (void *)MVMAP2315_PHY0_BASE; +static struct mvmap2315_dphy_regs * const mvmap2315_dphy1 + = (void *)MVMAP2315_PHY1_BASE; +static struct mvmap2315_dphy_regs * const mvmap2315_dphy2 + = (void *)MVMAP2315_PHY2_BASE; +static struct mvmap2315_dphy_regs * const mvmap2315_dphy3 + = (void *)MVMAP2315_PHY3_BASE; + +#define MVMAP2315_MC_DRAM_READY BIT(0) +struct mvmap2315_mc_regs { + u32 mc_id; + u32 mc_status_ch0; + u32 dram_status; + u8 reserved0[0x04]; + u32 mc_status_ch1; + u32 mc_status_ch2; + u32 mc_status_ch3; + u32 dram_status1; + u32 user_command_0; + u32 user_command_1; + u32 user_command_2; + u32 user_command_3; + u8 reserved1[0x10]; + u32 sram_control; + u32 mc_control_0; + u32 exclusive_monitor; + u32 ras_control; + u32 spool_control; + u32 mc_pwr_ctl; + u32 wb_control; + u32 cat_priority_ctl; + u32 rob_control; + u32 rdp_control; + u32 axi_port_control; + u32 wb_control1; + u32 regtable_control; + u32 regtable_data_0; + u32 regtable_data_1; + u32 rz_access_ctl; + u32 tz_range0_low; + u32 tz_range0_high; + u32 tz_range1_low; + u32 tz_range1_high; + u32 tz_range2_low; + u32 tz_range2_high; + u32 tz_range3_low; + u32 tz_range3_high; + u32 tz_range4_low; + u32 tz_range4_high; + u32 tz_range5_low; + u32 tz_range5_high; + u32 tz_range6_low; + u32 tz_range6_high; + u32 tz_range7_low; + u32 tz_range7_high; + u32 tz_range8_low; + u32 tz_range8_high; + u32 tz_range9_low; + u32 tz_range9_high; + u32 tz_range10_low; + u32 tz_range10_high; + u32 tz_range11_low; + u32 tz_range11_high; + u32 tz_range12_low; + u32 tz_range12_high; + u32 tz_range13_low; + u32 tz_range13_high; + u32 tz_range14_low; + u32 tz_range14_high; + u32 tz_range15_low; + u32 tz_range15_high; + u32 pc_config0; + u32 pc_config1; + u32 pc_status; + u32 pc_control; + u32 pc0; + u32 pc1; + u32 pc2; + u32 pc3; + u32 pc4; + u32 pc5; + u32 pc6; + u32 pc7; + u8 reserved2[0x10]; + u32 isr; + u32 ier; + u8 reserved3[0x08]; + u32 adc_err_id; + u32 adc_err_adr_l; + u32 adc_err_adr_h; + u8 reserved4[0x04]; + u32 am_period; + u32 am_th; + u8 reserved5[0x08]; + u32 am2_period; + u32 am2_low_th; + u32 am2_high_th; + u32 am2_busy_cycle; + u32 rpp_starvation_control; + u32 bw_allocation_tc_window0; + u32 bw_allocation_tc_window1; + u32 bw_allocation_tc_window2; + u32 bw_allocation_tc_window3; + u32 bw_allocation_tc_window4; + u32 bw_allocation_tc_window5; + u32 bw_allocation_tc_window6; + u32 bw_allocation_tc_window7; + u32 bw_allocation_tc_window8; + u32 bw_allocation_tc_window9; + u32 bw_allocation_tc_window10; + u32 bw_allocation_tc_window11; + u32 bw_allocation_tc_window12; + u32 bw_allocation_tc_window13; + u32 bw_allocation_tc_window14; + u32 bw_allocation_tc_window15; + u32 cat_priority_ctl_ddr4; + u8 reserved6[0x38]; + u32 mmap0_low_ch0; + u32 mmap0_high_ch0; + u32 mmap1_low_ch0; + u32 mmap1_high_ch0; + u8 reserved7[0x10]; + u32 ch0_mc_config_cs0; + u32 ch0_mc_config_cs1; + u8 reserved8[0x98]; + u32 ch0_mc_control_1; + u32 ch0_mc_control_2; + u32 ch0_mc_control_3; + u32 ch0_mc_control_4; + u8 reserved9[0x30]; + u32 ch0_dram_config_1; + u32 ch0_dram_config_2; + u32 ch0_dram_config_3; + u32 ch0_dram_config_4; + u32 ch0_dram_config_5_cs0; + u32 ch0_dram_config_5_cs1; + u8 reserved10[0x08]; + u32 ch0_dram_config_6; + u32 ch0_dram_config_7; + u32 ch0_dram_config_8; + u32 ch0_dram_config_9; + u32 ch0_dram_config_10; + u32 ch0_dram_config_11; + u32 ch0_dram_config_12; + u8 reserved11; + u32 ch0_odt_control_0; + u32 ch0_odt_control_1; + u32 ch0_odt_control_2; + u32 ch0_odt_control_3; + u32 ch0_rdimm_config_0; + u32 ch0_rdimm_config_1; + u32 ch0_rdimm_config_2; + u32 ch0_rdimm_config_3; + u8 reserved12[0x10]; + u32 ch0_mrr_data; + u8 reserved13[0x0c]; + u32 ch0_ddr_init_timing_control_0; + u32 ch0_ddr_init_timing_control_1; + u32 ch0_ddr_init_timing_control_2; + u32 ch0_zqc_timing_0; + u32 ch0_zqc_timing_1; + u32 ch0_refresh_timing; + u32 ch0_selfrefresh_timing_0; + u32 ch0_selfrefresh_timing_1; + u32 ch0_powerdown_timing_0; + u32 ch0_powerdown_timing_1; + u32 ch0_mrs_timing; + u32 ch0_act_timing; + u32 ch0_precharge_timing; + u32 ch0_cas_ras_timing_0; + u32 ch0_cas_ras_timing_1; + u32 ch0_off_spec_timing_0; + u32 ch0_off_spec_timing_1; + u32 ch0_dram_read_timing; + u32 ch0_dram_ca_train_timing; + u8 reserved14[0x0c]; + u32 ch0_dram_training_timing; + u32 ch0_rdimm_timing_0; + u32 ch0_rdimm_timing_1; + u8 reserved15[0x1c]; + u32 mmap0_low_ch1; + u32 mmap0_high_ch1; + u32 mmap1_low_ch1; + u32 mmap1_high_ch1; + u8 reserved16[0x10]; + u32 ch1_mc_config_cs0; + u32 ch1_mc_config_cs1; + u8 reserved17[0x98]; + u32 ch1_mc_control_1; + u32 ch1_mc_control_2; + u32 ch1_mc_control_3; + u32 ch1_mc_control_4; + u8 reserved18[0x30]; + u32 ch1_dram_config_1; + u32 ch1_dram_config_2; + u32 ch1_dram_config_3; + u32 ch1_dram_config_4; + u32 ch1_dram_config_5_cs0; + u32 ch1_dram_config_5_cs1; + u8 reserved19[0x08]; + u32 ch1_dram_config_6; + u32 ch1_dram_config_7; + u32 ch1_dram_config_8; + u32 ch1_dram_config_9; + u32 ch1_dram_config_10; + u32 ch1_dram_config_11; + u32 ch1_dram_config_12; + u8 reserved20[0x04]; + u32 ch1_odt_control_0; + u32 ch1_odt_control_1; + u32 ch1_odt_control_2; + u32 ch1_odt_control_3; + u32 ch1_rdimm_config_0; + u32 ch1_rdimm_config_1; + u32 ch1_rdimm_config_2; + u32 ch1_rdimm_config_3; + u8 reserved21[0x10]; + u32 ch1_mrr_data; + u8 reserved22[0x0c]; + u32 ch1_ddr_init_timing_control_0; + u32 ch1_ddr_init_timing_control_1; + u32 ch1_ddr_init_timing_control_2; + u32 ch1_zqc_timing_0; + u32 ch1_zqc_timing_1; + u32 ch1_refresh_timing; + u32 ch1_selfrefresh_timing_0; + u32 ch1_selfrefresh_timing_1; + u32 ch1_powerdown_timing_0; + u32 ch1_powerdown_timing_1; + u32 ch1_mrs_timing; + u32 ch1_act_timing; + u32 ch1_precharge_timing; + u32 ch1_cas_ras_timing_0; + u32 ch1_cas_ras_timing_1; + u32 ch1_off_spec_timing_0; + u32 ch1_off_spec_timing_1; + u32 ch1_dram_read_timing; + u32 ch1_dram_ca_train_timing; + u8 reserved23[0x0c]; + u32 ch1_dram_training_timing; + u32 ch1_rdimm_timing_0; + u32 ch1_rdimm_timing_1; + u8 reserved24[0x1c]; + u32 mmap0_low_ch2; + u32 mmap0_high_ch2; + u32 mmap1_low_ch2; + u32 mmap1_high_ch2; + u8 reserved25[0x10]; + u32 ch2_mc_config_cs0; + u32 ch2_mc_config_cs1; + u8 reserved26[0x98]; + u32 ch2_mc_control_1; + u32 ch2_mc_control_2; + u32 ch2_mc_control_3; + u32 ch2_mc_control_4; + u8 reserved27[0x30]; + u32 ch2_dram_config_1; + u32 ch2_dram_config_2; + u32 ch2_dram_config_3; + u32 ch2_dram_config_4; + u32 ch2_dram_config_5_cs0; + u32 ch2_dram_config_5_cs1; + u8 reserved28[0x08]; + u32 ch2_dram_config_6; + u32 ch2_dram_config_7; + u32 ch2_dram_config_8; + u32 ch2_dram_config_9; + u32 ch2_dram_config_10; + u32 ch2_dram_config_11; + u32 ch2_dram_config_12; + u8 reserved29[0x04]; + u32 ch2_odt_control_0; + u32 ch2_odt_control_1; + u32 ch2_odt_control_2; + u32 ch2_odt_control_3; + u32 ch2_rdimm_config_0; + u32 ch2_rdimm_config_1; + u32 ch2_rdimm_config_2; + u32 ch2_rdimm_config_3; + u8 reserved30[0x10]; + u32 ch2_mrr_data; + u8 reserved31[0x0c]; + u32 ch2_ddr_init_timing_control_0; + u32 ch2_ddr_init_timing_control_1; + u32 ch2_ddr_init_timing_control_2; + u32 ch2_zqc_timing_0; + u32 ch2_zqc_timing_1; + u32 ch2_refresh_timing; + u32 ch2_selfrefresh_timing_0; + u32 ch2_selfrefresh_timing_1; + u32 ch2_powerdown_timing_0; + u32 ch2_powerdown_timing_1; + u32 ch2_mrs_timing; + u32 ch2_act_timing; + u32 ch2_precharge_timing; + u32 ch2_cas_ras_timing_0; + u32 ch2_cas_ras_timing_1; + u32 ch2_off_spec_timing_0; + u32 ch2_off_spec_timing_1; + u32 ch2_dram_read_timing; + u32 ch2_dram_ca_train_timing; + u8 reserved32[0x0c]; + u32 ch2_dram_training_timing; + u32 ch2_rdimm_timing_0; + u32 ch2_rdimm_timing_1; + u8 reserved33[0x1c]; + u32 mmap0_low_ch3; + u32 mmap0_high_ch3; + u32 mmap1_low_ch3; + u32 mmap1_high_ch3; + u8 reserved34[0x10]; + u32 ch3_mc_config_cs0; + u32 ch3_mc_config_cs1; + u8 reserved35[0x98]; + u32 ch3_mc_control_1; + u32 ch3_mc_control_2; + u32 ch3_mc_control_3; + u32 ch3_mc_control_4; + u8 reserved36[0x30]; + u32 ch3_dram_config_1; + u32 ch3_dram_config_2; + u32 ch3_dram_config_3; + u32 ch3_dram_config_4; + u32 ch3_dram_config_5_cs0; + u32 ch3_dram_config_5_cs1; + u8 reserved37[0x08]; + u32 ch3_dram_config_6; + u32 ch3_dram_config_7; + u32 ch3_dram_config_8; + u32 ch3_dram_config_9; + u32 ch3_dram_config_10; + u32 ch3_dram_config_11; + u32 ch3_dram_config_12; + u8 reserved38[0x04]; + u32 ch3_odt_control_0; + u32 ch3_odt_control_1; + u32 ch3_odt_control_2; + u32 ch3_odt_control_3; + u32 ch3_rdimm_config_0; + u32 ch3_rdimm_config_1; + u32 ch3_rdimm_config_2; + u32 ch3_rdimm_config_3; + u8 reserved39[0x10]; + u32 ch3_mrr_data; + u8 reserved40[0x0c]; + u32 ch3_ddr_init_timing_control_0; + u32 ch3_ddr_init_timing_control_1; + u32 ch3_ddr_init_timing_control_2; + u32 ch3_zqc_timing_0; + u32 ch3_zqc_timing_1; + u32 ch3_refresh_timing; + u32 ch3_selfrefresh_timing_0; + u32 ch3_selfrefresh_timing_1; + u32 ch3_powerdown_timing_0; + u32 ch3_powerdown_timing_1; + u32 ch3_mrs_timing; + u32 ch3_act_timing; + u32 ch3_precharge_timing; + u32 ch3_cas_ras_timing_0; + u32 ch3_cas_ras_timing_1; + u32 ch3_off_spec_timing_0; + u32 ch3_off_spec_timing_1; + u32 ch3_dram_read_timing; + u32 ch3_dram_ca_train_timing; + u8 reserved41[0x0c]; + u32 ch3_dram_training_timing; + u32 ch3_rdimm_timing_0; + u32 ch3_rdimm_timing_1; + u8 reserved42[0x6c]; + u32 test_control; + u8 reserved43[0x0c]; + u32 user_trigger_ir; + u8 reserved44[0x08]; + u32 training_control; + u32 training_pattern0; + u32 training_pattern1; + u32 training_pattern2; + u32 training_pattern3; + u32 training_pattern4; + u32 training_pattern5; + u32 training_pattern6; + u32 training_pattern7; + u32 dmi_training_pattern; + u8 reserved45[0x93c]; + u32 dfi_phy_user_command_0; + u8 reserved46[0x0c]; + u32 ch0_dfi_phy_control_0; + u32 ch0_dfi_phy_control_1; + u32 ch0_dfi_phy_control_2; + u32 ch0_dfi_phy_control_3; + u32 ch0_dfi_phy_ca_train; + u32 ch0_dfi_phy_ca_pattern; + u32 ch0_dfi_phy_write_dq_train; + u32 ch0_dfi_phy_leveling_status; + u8 reserved47[0x3e0]; + u32 ch1_dfi_phy_control_0; + u32 ch1_dfi_phy_control_1; + u32 ch1_dfi_phy_control_2; + u32 ch1_dfi_phy_control_3; + u32 ch1_dfi_phy_ca_train; + u32 ch1_dfi_phy_ca_pattern; + u32 ch1_dfi_phy_write_dq_train; + u32 ch1_dfi_phy_leveling_status; + u8 reserved48[0x3e0]; + u32 ch2_dfi_phy_control_0; + u32 ch2_dfi_phy_control_1; + u32 ch2_dfi_phy_control_2; + u32 ch2_dfi_phy_control_3; + u32 ch2_dfi_phy_ca_train; + u32 ch2_dfi_phy_ca_pattern; + u32 ch2_dfi_phy_write_dq_train; + u32 ch2_dfi_phy_leveling_status; + u8 reserved49[0x3e0]; + u32 ch3_dfi_phy_control_0; + u32 ch3_dfi_phy_control_1; + u32 ch3_dfi_phy_control_2; + u32 ch3_dfi_phy_control_3; + u32 ch3_dfi_phy_ca_train; + u32 ch3_dfi_phy_ca_pattern; + u32 ch3_dfi_phy_write_dq_train; + u32 ch3_dfi_phy_leveling_status; +}; + +check_member(mvmap2315_mc_regs, ch3_dfi_phy_leveling_status, 0x1FFC); +static struct mvmap2315_mc_regs * const mvmap2315_mc + = (void *)MVMAP2315_MC_BASE; + +void sdram_init(struct mvmap2315_sdram_params *sdram_params); size_t sdram_size_mb(void);
#endif /* __SOC_MARVELL_MVMAP2315_SDRAM_H__ */ diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index cffa8d0..09347c0 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -25,6 +25,9 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> +#include <soc/sdram.h> + +extern struct mvmap2315_sdram_params ddr_params;
void main(void) { @@ -34,6 +37,8 @@ void main(void)
clock_init();
+ sdram_init(&ddr_params); + write32((void *)MVMAP2315_BOOTBLOCK_CB1, 0x4);
while (read32((void *)MVMAP2315_BOOTBLOCK_CB2) != 0x4) diff --git a/src/soc/marvell/mvmap2315/sdram.c b/src/soc/marvell/mvmap2315/sdram.c index 2d17137..62b8c32 100644 --- a/src/soc/marvell/mvmap2315/sdram.c +++ b/src/soc/marvell/mvmap2315/sdram.c @@ -17,8 +17,466 @@ #include <stdint.h> #include <stdlib.h>
+#include <arch/io.h> +#include <console/console.h> #include <soc/sdram.h>
+void sdram_init(struct mvmap2315_sdram_params *sdram_params) +{ + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + write32(&mvmap2315_dphy0->dphy_dll_ctrl_0, + sdram_params->dphy_params[0]); + write32(&mvmap2315_dphy0->dphy_dll_ctrl0, + sdram_params->dphy_params[1]); + write32(&mvmap2315_dphy0->dphy_dll_ctrl0, + sdram_params->dphy_params[2]); + write32(&mvmap2315_dphy1->dphy_dll_ctrl_0, + sdram_params->dphy_params[3]); + write32(&mvmap2315_dphy1->dphy_dll_ctrl0, + sdram_params->dphy_params[4]); + write32(&mvmap2315_dphy1->dphy_dll_ctrl0, + sdram_params->dphy_params[5]); + write32(&mvmap2315_dphy2->dphy_dll_ctrl_0, + sdram_params->dphy_params[6]); + write32(&mvmap2315_dphy2->dphy_dll_ctrl0, + sdram_params->dphy_params[7]); + write32(&mvmap2315_dphy2->dphy_dll_ctrl0, + sdram_params->dphy_params[8]); + write32(&mvmap2315_dphy3->dphy_dll_ctrl_0, + sdram_params->dphy_params[9]); + write32(&mvmap2315_dphy3->dphy_dll_ctrl0, + sdram_params->dphy_params[10]); + write32(&mvmap2315_dphy3->dphy_dll_ctrl0, + sdram_params->dphy_params[11]); + write32(&mvmap2315_dphy0->dphy_dll_ctrl0, + sdram_params->dphy_params[12]); + write32(&mvmap2315_dphy0->dphy_dll_ctrl0, + sdram_params->dphy_params[13]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl2, + sdram_params->dphy_params[14]); + write32(&mvmap2315_dphy1->dphy_dll_ctrl0, + sdram_params->dphy_params[15]); + write32(&mvmap2315_dphy1->dphy_dll_ctrl0, + sdram_params->dphy_params[16]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl2, + sdram_params->dphy_params[17]); + write32(&mvmap2315_dphy2->dphy_dll_ctrl0, + sdram_params->dphy_params[18]); + write32(&mvmap2315_dphy2->dphy_dll_ctrl0, + sdram_params->dphy_params[19]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl2, + sdram_params->dphy_params[20]); + write32(&mvmap2315_dphy3->dphy_dll_ctrl0, + sdram_params->dphy_params[21]); + write32(&mvmap2315_dphy3->dphy_dll_ctrl0, + sdram_params->dphy_params[22]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl2, + sdram_params->dphy_params[23]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl4, + sdram_params->dphy_params[24]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl4, + sdram_params->dphy_params[25]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl4, + sdram_params->dphy_params[26]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl4, + sdram_params->dphy_params[27]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl4, + sdram_params->dphy_params[28]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl4, + sdram_params->dphy_params[29]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl4, + sdram_params->dphy_params[30]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl4, + sdram_params->dphy_params[31]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl4, + sdram_params->dphy_params[32]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl4, + sdram_params->dphy_params[33]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl4, + sdram_params->dphy_params[34]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl4, + sdram_params->dphy_params[35]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl4, + sdram_params->dphy_params[36]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl4, + sdram_params->dphy_params[37]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl4, + sdram_params->dphy_params[38]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl4, + sdram_params->dphy_params[39]); + write32(&mvmap2315_mc->ch0_mc_config_cs0, + sdram_params->mc_params[0]); + write32(&mvmap2315_mc->ch1_mc_config_cs0, + sdram_params->mc_params[1]); + write32(&mvmap2315_mc->ch2_mc_config_cs0, + sdram_params->mc_params[2]); + write32(&mvmap2315_mc->ch3_mc_config_cs0, + sdram_params->mc_params[3]); + write32(&mvmap2315_mc->ch0_mc_config_cs1, + sdram_params->mc_params[4]); + write32(&mvmap2315_mc->ch1_mc_config_cs1, + sdram_params->mc_params[5]); + write32(&mvmap2315_mc->ch2_mc_config_cs1, + sdram_params->mc_params[6]); + write32(&mvmap2315_mc->ch3_mc_config_cs1, + sdram_params->mc_params[7]); + write32(&mvmap2315_mc->ch0_dram_config_4, + sdram_params->mc_params[8]); + write32(&mvmap2315_mc->ch1_dram_config_4, + sdram_params->mc_params[9]); + write32(&mvmap2315_mc->ch2_dram_config_4, + sdram_params->mc_params[10]); + write32(&mvmap2315_mc->ch3_dram_config_4, + sdram_params->mc_params[11]); + write32(&mvmap2315_mc->ch0_dram_config_5_cs0, + sdram_params->mc_params[12]); + write32(&mvmap2315_mc->ch1_dram_config_5_cs0, + sdram_params->mc_params[13]); + write32(&mvmap2315_mc->ch2_dram_config_5_cs0, + sdram_params->mc_params[14]); + write32(&mvmap2315_mc->ch3_dram_config_5_cs0, + sdram_params->mc_params[15]); + write32(&mvmap2315_mc->ch0_dram_config_5_cs1, + sdram_params->mc_params[16]); + write32(&mvmap2315_mc->ch1_dram_config_5_cs1, + sdram_params->mc_params[17]); + write32(&mvmap2315_mc->ch2_dram_config_5_cs1, + sdram_params->mc_params[18]); + write32(&mvmap2315_mc->ch3_dram_config_5_cs1, + sdram_params->mc_params[19]); + write32(&mvmap2315_mc->mmap0_high_ch0, + sdram_params->mc_params[20]); + write32(&mvmap2315_mc->mmap0_low_ch0, + sdram_params->mc_params[21]); + write32(&mvmap2315_mc->mmap0_high_ch1, + sdram_params->mc_params[22]); + write32(&mvmap2315_mc->mmap0_low_ch1, + sdram_params->mc_params[23]); + write32(&mvmap2315_mc->mmap0_high_ch2, + sdram_params->mc_params[24]); + write32(&mvmap2315_mc->mmap0_low_ch2, + sdram_params->mc_params[25]); + write32(&mvmap2315_mc->mmap0_high_ch3, + sdram_params->mc_params[26]); + write32(&mvmap2315_mc->mmap0_low_ch3, + sdram_params->mc_params[27]); + write32(&mvmap2315_mc->mmap1_high_ch0, + sdram_params->mc_params[28]); + write32(&mvmap2315_mc->mmap1_low_ch0, + sdram_params->mc_params[29]); + write32(&mvmap2315_mc->mmap1_high_ch1, + sdram_params->mc_params[30]); + write32(&mvmap2315_mc->mmap1_low_ch1, + sdram_params->mc_params[31]); + write32(&mvmap2315_mc->mmap1_high_ch2, + sdram_params->mc_params[32]); + write32(&mvmap2315_mc->mmap1_low_ch2, + sdram_params->mc_params[33]); + write32(&mvmap2315_mc->mmap1_high_ch3, + sdram_params->mc_params[34]); + write32(&mvmap2315_mc->mmap1_low_ch3, + sdram_params->mc_params[35]); + write32(&mvmap2315_mc->ch0_precharge_timing, + sdram_params->mc_params[36]); + write32(&mvmap2315_mc->ch1_precharge_timing, + sdram_params->mc_params[37]); + write32(&mvmap2315_mc->ch2_precharge_timing, + sdram_params->mc_params[38]); + write32(&mvmap2315_mc->ch3_precharge_timing, + sdram_params->mc_params[39]); + write32(&mvmap2315_mc->ch0_act_timing, + sdram_params->mc_params[40]); + write32(&mvmap2315_mc->ch1_act_timing, + sdram_params->mc_params[41]); + write32(&mvmap2315_mc->ch2_act_timing, + sdram_params->mc_params[42]); + write32(&mvmap2315_mc->ch3_act_timing, + sdram_params->mc_params[43]); + write32(&mvmap2315_mc->ch0_cas_ras_timing_0, + sdram_params->mc_params[44]); + write32(&mvmap2315_mc->ch1_cas_ras_timing_0, + sdram_params->mc_params[45]); + write32(&mvmap2315_mc->ch2_cas_ras_timing_0, + sdram_params->mc_params[46]); + write32(&mvmap2315_mc->ch3_cas_ras_timing_0, + sdram_params->mc_params[47]); + write32(&mvmap2315_mc->ch0_cas_ras_timing_1, + sdram_params->mc_params[48]); + write32(&mvmap2315_mc->ch1_cas_ras_timing_1, + sdram_params->mc_params[49]); + write32(&mvmap2315_mc->ch2_cas_ras_timing_1, + sdram_params->mc_params[50]); + write32(&mvmap2315_mc->ch3_cas_ras_timing_1, + sdram_params->mc_params[51]); + write32(&mvmap2315_mc->ch0_mrs_timing, + sdram_params->mc_params[52]); + write32(&mvmap2315_mc->ch1_mrs_timing, + sdram_params->mc_params[53]); + write32(&mvmap2315_mc->ch2_mrs_timing, + sdram_params->mc_params[54]); + write32(&mvmap2315_mc->ch3_mrs_timing, + sdram_params->mc_params[55]); + write32(&mvmap2315_mc->ch0_ddr_init_timing_control_0, + sdram_params->mc_params[56]); + write32(&mvmap2315_mc->ch0_ddr_init_timing_control_1, + sdram_params->mc_params[57]); + write32(&mvmap2315_mc->ch0_ddr_init_timing_control_2, + sdram_params->mc_params[58]); + write32(&mvmap2315_mc->ch1_ddr_init_timing_control_0, + sdram_params->mc_params[59]); + write32(&mvmap2315_mc->ch1_ddr_init_timing_control_1, + sdram_params->mc_params[60]); + write32(&mvmap2315_mc->ch1_ddr_init_timing_control_2, + sdram_params->mc_params[61]); + write32(&mvmap2315_mc->ch2_ddr_init_timing_control_0, + sdram_params->mc_params[62]); + write32(&mvmap2315_mc->ch2_ddr_init_timing_control_1, + sdram_params->mc_params[63]); + write32(&mvmap2315_mc->ch2_ddr_init_timing_control_2, + sdram_params->mc_params[64]); + write32(&mvmap2315_mc->ch3_ddr_init_timing_control_0, + sdram_params->mc_params[65]); + write32(&mvmap2315_mc->ch3_ddr_init_timing_control_1, + sdram_params->mc_params[66]); + write32(&mvmap2315_mc->ch3_ddr_init_timing_control_2, + sdram_params->mc_params[67]); + write32(&mvmap2315_mc->ch0_off_spec_timing_0, + sdram_params->mc_params[68]); + write32(&mvmap2315_mc->ch1_off_spec_timing_0, + sdram_params->mc_params[69]); + write32(&mvmap2315_mc->ch2_off_spec_timing_0, + sdram_params->mc_params[70]); + write32(&mvmap2315_mc->ch3_off_spec_timing_0, + sdram_params->mc_params[71]); + write32(&mvmap2315_mc->ch0_off_spec_timing_1, + sdram_params->mc_params[72]); + write32(&mvmap2315_mc->ch1_off_spec_timing_1, + sdram_params->mc_params[73]); + write32(&mvmap2315_mc->ch2_off_spec_timing_1, + sdram_params->mc_params[74]); + write32(&mvmap2315_mc->ch3_off_spec_timing_1, + sdram_params->mc_params[75]); + write32(&mvmap2315_mc->ch0_dram_read_timing, + sdram_params->mc_params[76]); + write32(&mvmap2315_mc->ch1_dram_read_timing, + sdram_params->mc_params[77]); + write32(&mvmap2315_mc->ch2_dram_read_timing, + sdram_params->mc_params[78]); + write32(&mvmap2315_mc->ch3_dram_read_timing, + sdram_params->mc_params[79]); + write32(&mvmap2315_mc->ch0_refresh_timing, + sdram_params->mc_params[80]); + write32(&mvmap2315_mc->ch1_refresh_timing, + sdram_params->mc_params[81]); + write32(&mvmap2315_mc->ch2_refresh_timing, + sdram_params->mc_params[82]); + write32(&mvmap2315_mc->ch3_refresh_timing, + sdram_params->mc_params[83]); + write32(&mvmap2315_mc->ch0_selfrefresh_timing_0, + sdram_params->mc_params[84]); + write32(&mvmap2315_mc->ch1_selfrefresh_timing_0, + sdram_params->mc_params[85]); + write32(&mvmap2315_mc->ch2_selfrefresh_timing_0, + sdram_params->mc_params[86]); + write32(&mvmap2315_mc->ch3_selfrefresh_timing_0, + sdram_params->mc_params[87]); + write32(&mvmap2315_mc->ch0_powerdown_timing_0, + sdram_params->mc_params[88]); + write32(&mvmap2315_mc->ch1_powerdown_timing_0, + sdram_params->mc_params[89]); + write32(&mvmap2315_mc->ch2_powerdown_timing_0, + sdram_params->mc_params[90]); + write32(&mvmap2315_mc->ch3_powerdown_timing_0, + sdram_params->mc_params[91]); + write32(&mvmap2315_mc->ch0_odt_control_1, + sdram_params->mc_params[92]); + write32(&mvmap2315_mc->ch1_odt_control_1, + sdram_params->mc_params[93]); + write32(&mvmap2315_mc->ch2_odt_control_1, + sdram_params->mc_params[94]); + write32(&mvmap2315_mc->ch3_odt_control_1, + sdram_params->mc_params[95]); + write32(&mvmap2315_mc->ch0_odt_control_2, + sdram_params->mc_params[96]); + write32(&mvmap2315_mc->ch1_odt_control_2, + sdram_params->mc_params[97]); + write32(&mvmap2315_mc->ch2_odt_control_2, + sdram_params->mc_params[98]); + write32(&mvmap2315_mc->ch3_odt_control_2, + sdram_params->mc_params[99]); + write32(&mvmap2315_mc->ch0_dram_config_1, + sdram_params->mc_params[100]); + write32(&mvmap2315_mc->ch1_dram_config_1, + sdram_params->mc_params[101]); + write32(&mvmap2315_mc->ch2_dram_config_1, + sdram_params->mc_params[102]); + write32(&mvmap2315_mc->ch3_dram_config_1, + sdram_params->mc_params[103]); + write32(&mvmap2315_mc->mc_control_0, + sdram_params->mc_params[104]); + write32(&mvmap2315_mc->ch0_mc_control_2, + sdram_params->mc_params[105]); + write32(&mvmap2315_mc->ch1_mc_control_2, + sdram_params->mc_params[106]); + write32(&mvmap2315_mc->ch2_mc_control_2, + sdram_params->mc_params[107]); + write32(&mvmap2315_mc->ch3_mc_control_2, + sdram_params->mc_params[108]); + write32(&mvmap2315_mc->ch0_dram_config_2, + sdram_params->mc_params[109]); + write32(&mvmap2315_mc->ch1_dram_config_2, + sdram_params->mc_params[110]); + write32(&mvmap2315_mc->ch2_dram_config_2, + sdram_params->mc_params[111]); + write32(&mvmap2315_mc->ch3_dram_config_2, + sdram_params->mc_params[112]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl0, + sdram_params->dphy_params[40]); + write32(&mvmap2315_dphy0->dphy_dfi_ctrl0, + sdram_params->dphy_params[41]); + write32(&mvmap2315_dphy0->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[42]); + write32(&mvmap2315_dphy0->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[43]); + write32(&mvmap2315_dphy0->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[44]); + write32(&mvmap2315_dphy0->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[45]); + write32(&mvmap2315_dphy0->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[46]); + write32(&mvmap2315_dphy0->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[47]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl0, + sdram_params->dphy_params[48]); + write32(&mvmap2315_dphy1->dphy_dfi_ctrl0, + sdram_params->dphy_params[49]); + write32(&mvmap2315_dphy1->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[50]); + write32(&mvmap2315_dphy1->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[51]); + write32(&mvmap2315_dphy1->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[52]); + write32(&mvmap2315_dphy1->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[53]); + write32(&mvmap2315_dphy1->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[54]); + write32(&mvmap2315_dphy1->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[55]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl0, + sdram_params->dphy_params[56]); + write32(&mvmap2315_dphy2->dphy_dfi_ctrl0, + sdram_params->dphy_params[57]); + write32(&mvmap2315_dphy2->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[58]); + write32(&mvmap2315_dphy2->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[59]); + write32(&mvmap2315_dphy2->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[60]); + write32(&mvmap2315_dphy2->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[61]); + write32(&mvmap2315_dphy2->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[62]); + write32(&mvmap2315_dphy2->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[63]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl0, + sdram_params->dphy_params[64]); + write32(&mvmap2315_dphy3->dphy_dfi_ctrl0, + sdram_params->dphy_params[65]); + write32(&mvmap2315_dphy3->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[66]); + write32(&mvmap2315_dphy3->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[67]); + write32(&mvmap2315_dphy3->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[68]); + write32(&mvmap2315_dphy3->dphy_dq_pad_ctrl2, + sdram_params->dphy_params[69]); + write32(&mvmap2315_dphy3->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[70]); + write32(&mvmap2315_dphy3->dphy_adcm_pad_ctrl2, + sdram_params->dphy_params[71]); + write32(&mvmap2315_mc->ch0_dfi_phy_control_1, + sdram_params->mc_params[113]); + write32(&mvmap2315_mc->ch1_dfi_phy_control_1, + sdram_params->mc_params[114]); + write32(&mvmap2315_mc->ch2_dfi_phy_control_1, + sdram_params->mc_params[115]); + write32(&mvmap2315_mc->ch3_dfi_phy_control_1, + sdram_params->mc_params[116]); + write32(&mvmap2315_dphy0->dphy_vref_ctrl0, + sdram_params->dphy_params[72]); + write32(&mvmap2315_dphy0->dphy_vref_ctrl0, + sdram_params->dphy_params[73]); + write32(&mvmap2315_dphy1->dphy_vref_ctrl0, + sdram_params->dphy_params[74]); + write32(&mvmap2315_dphy1->dphy_vref_ctrl0, + sdram_params->dphy_params[75]); + write32(&mvmap2315_dphy2->dphy_vref_ctrl0, + sdram_params->dphy_params[76]); + write32(&mvmap2315_dphy2->dphy_vref_ctrl0, + sdram_params->dphy_params[77]); + write32(&mvmap2315_dphy3->dphy_vref_ctrl0, + sdram_params->dphy_params[78]); + write32(&mvmap2315_dphy3->dphy_vref_ctrl0, + sdram_params->dphy_params[79]); + write32(&mvmap2315_mc->mc_pwr_ctl, + sdram_params->mc_params[117]); + write32(&mvmap2315_mc->user_command_0, + sdram_params->mc_params[118]); + + while (!(read32(&mvmap2315_mc->dram_status) & MVMAP2315_MC_DRAM_READY)) + ; + + write32(&mvmap2315_dphy0->dphy_qsg_ctrl0, + sdram_params->dphy_params[80]); + write32(&mvmap2315_dphy0->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[81]); + write32(&mvmap2315_dphy0->dphy_qsg_ctrl0, + sdram_params->dphy_params[82]); + write32(&mvmap2315_dphy0->dphy_qsg_ctrl0, + sdram_params->dphy_params[83]); + write32(&mvmap2315_dphy0->dphy_qsg_ctrl0, + sdram_params->dphy_params[84]); + write32(&mvmap2315_dphy1->dphy_qsg_ctrl0, + sdram_params->dphy_params[85]); + write32(&mvmap2315_dphy1->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[86]); + write32(&mvmap2315_dphy1->dphy_qsg_ctrl0, + sdram_params->dphy_params[87]); + write32(&mvmap2315_dphy1->dphy_qsg_ctrl0, + sdram_params->dphy_params[88]); + write32(&mvmap2315_dphy1->dphy_qsg_ctrl0, + sdram_params->dphy_params[89]); + write32(&mvmap2315_dphy2->dphy_qsg_ctrl0, + sdram_params->dphy_params[90]); + write32(&mvmap2315_dphy2->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[91]); + write32(&mvmap2315_dphy2->dphy_qsg_ctrl0, + sdram_params->dphy_params[92]); + write32(&mvmap2315_dphy2->dphy_qsg_ctrl0, + sdram_params->dphy_params[93]); + write32(&mvmap2315_dphy2->dphy_qsg_ctrl0, + sdram_params->dphy_params[94]); + write32(&mvmap2315_dphy3->dphy_qsg_ctrl0, + sdram_params->dphy_params[95]); + write32(&mvmap2315_dphy3->dphy_dq_pad_ctrl0, + sdram_params->dphy_params[96]); + write32(&mvmap2315_dphy3->dphy_qsg_ctrl0, + sdram_params->dphy_params[97]); + write32(&mvmap2315_dphy3->dphy_qsg_ctrl0, + sdram_params->dphy_params[98]); + write32(&mvmap2315_dphy3->dphy_qsg_ctrl0, + sdram_params->dphy_params[99]); + write32(&mvmap2315_mc->user_command_1, + sdram_params->mc_params[119]); + write32(&mvmap2315_mc->user_command_1, + sdram_params->mc_params[120]); + write32(&mvmap2315_mc->user_command_1, + sdram_params->mc_params[121]); + + printk(BIOS_DEBUG, "Exiting %s\n", __func__); +} + size_t sdram_size_mb(void) { return CONFIG_DRAM_SIZE_MB;