Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9402
-gerrit
commit 98fe3cf98aac14356b5d15a697ff5e15352958de Author: Dan Ehrenberg dehrenberg@chromium.org Date: Thu Oct 23 17:46:39 2014 -0700
storm: Initialize clock, pinmux for NAND if present on board
This patch runs basic NAND initialization code on Proto 0.2 boards which have been reworked for NAND. It makes sense to do this in coreboot for two reasons: - In general, it is reasonable for coreboot to initialize clocks and such in preparation for depthcharge's use. Waiting times can be pooled, and the initialization itself here is very fast. - There is a kernel bug which requires that the clock already be initialized before the kernel loads NAND support. Coreboot is a more sensible place to put a workaround than depthcharge because depthcharge initializes things lazily, but when booting from USB, depthcharge won't need to look at NAND. Partner bug 33270 This change involves bringing in an additional header file, ebi2.h, from uBoot.
TEST=Booted a kernel from USB and verified that NAND came up without any depthcharge hacks, whereas previously a USB-booted kernel would be unable to access NAND even with the same drivers compiled in due to an initialization failure. BUG=chromium:403432 BRANCH=none
Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c Original-Signed-off-by: Dan Ehrenberg dehrenberg@chromium.org Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c Original-Reviewed-on: https://chromium-review.googlesource.com/225277 Original-Reviewed-by: Vadim Bendebury vbendeb@chromium.org --- src/mainboard/google/storm/cdp.c | 28 +++++----- src/mainboard/google/storm/mainboard.c | 2 + src/soc/qualcomm/ipq806x/include/soc/cdp.h | 11 +++- src/soc/qualcomm/ipq806x/include/soc/ebi2.h | 80 +++++++++++++++++++++++++++++ 4 files changed, 107 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 78edb26..fd90689 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -3,7 +3,10 @@
#include <gpio.h> #include <soc/cdp.h> +#include <soc/ebi2.h> +#include <soc/clock.h> #include <types.h> +#include <boardid.h>
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) { @@ -204,6 +207,8 @@ void reset_cpu(ulong addr) for(;;); }
+#endif + static void configure_nand_gpio(void) { /* EBI2 CS, CLE, ALE, WE, OE */ @@ -230,25 +235,22 @@ static void configure_nand_gpio(void) void board_nand_init(void) { struct ebi2cr_regs *ebi2_regs; - extern int ipq_spi_init(void);
- if (gboard_param->flashdesc != NOR_MMC) { + if (board_id() != BOARD_ID_PROTO_0_2_NAND) + return;
- ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE; + ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
- nand_clock_config(); - configure_nand_gpio(); + nand_clock_config(); + configure_nand_gpio();
- /* NAND Flash is connected to CS0 */ - clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, - CS0_CFG_SERIAL_FLASH_DEVICE); - - ipq_nand_init(IPQ_NAND_LAYOUT_LINUX); - } - - ipq_spi_init(); + /* NAND Flash is connected to CS0 */ + clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, + CS0_CFG_SERIAL_FLASH_DEVICE); }
+#if 0 + void ipq_get_part_details(void) { int ret, i; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index a7062b2..5ff0b13 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -114,6 +114,8 @@ static void mainboard_init(device_t dev) setup_usb(); deassert_sw_reset(); setup_tpm(); + /* Functionally a 0-cost no-op if NAND is not present */ + board_nand_init(); }
static void mainboard_enable(device_t dev) diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index c7de23f..bb2151c 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -106,6 +106,12 @@ typedef struct {
#define IPQ_GMAC_NMACS 4
+enum storm_board_id { + BOARD_ID_PROTO_0 = 0, + BOARD_ID_PROTO_0_2 = 1, + BOARD_ID_PROTO_0_2_NAND = 26, +}; + /* Board specific parameters */ typedef struct { #if 0 @@ -136,4 +142,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
unsigned int get_board_index(unsigned machid); void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); -#endif + +void board_nand_init(void); + +#endif /* _IPQ806X_CDP_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h new file mode 100644 index 0000000..23333c2 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ +#ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ +#define __SOC_QUALCOMM_IPQ806X_EBI2_H_ + +#define EBI2CR_BASE (0x1A600000) + +struct ebi2cr_regs { + uint32_t chip_select_cfg0; /* 0x00000000 */ + uint32_t cfg; /* 0x00000004 */ + uint32_t hw_info; /* 0x00000008 */ + uint8_t reserved0[20]; + uint32_t lcd_cfg0; /* 0x00000020 */ + uint32_t lcd_cfg1; /* 0x00000024 */ + uint8_t reserved1[8]; + uint32_t arbiter_cfg; /* 0x00000030 */ + uint8_t reserved2[28]; + uint32_t debug_sel; /* 0x00000050 */ + uint32_t crc_cfg; /* 0x00000054 */ + uint32_t crc_reminder_cfg; /* 0x00000058 */ + uint32_t nand_adm_mux; /* 0x0000005C */ + uint32_t mutex_addr_offset; /* 0x00000060 */ + uint32_t misr_value; /* 0x00000064 */ + uint32_t clkon_cfg; /* 0x00000068 */ + uint32_t core_clkon_cfg; /* 0x0000006C */ +}; + +/* Register: EBI2_CHIP_SELECT_CFG0 */ +#define CS7_CFG_MASK 0x00001000 +#define CS7_CFG_DISABLE 0x00000000 +#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000 +#define CS7_CFG(i) ((i) << 12) + +#define CS6_CFG_MASK 0x00000800 +#define CS6_CFG_DISABLE 0x00000000 +#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800 +#define CS6_CFG(i) ((i) << 11) + +#define ETM_CS_CFG_MASK 0x00000400 +#define ETM_CS_CFG_DISABLE 0x00000000 +#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400 +#define ETM_CS_CFG(i) ((i) << 10) + +#define CS5_CFG_MASK 0x00000300 +#define CS5_CFG_DISABLE 0x00000000 +#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100 +#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200 +#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300 +#define CS5_CFG(i) ((i) << 8) + +#define CS4_CFG_MASK 0x000000c0 +#define CS4_CFG_DISABLE 0x00000000 +#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040 +#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0 +#define CS4_CFG(i) ((i) << 6) + +#define CS3_CFG_MASK 0x00000020 +#define CS3_CFG_DISABLE 0x00000000 +#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020 +#define CS3_CFG(i) ((i) << 5) + +#define CS2_CFG_MASK 0x00000010 +#define CS2_CFG_DISABLE 0x00000000 +#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010 +#define CS2_CFG(i) ((i) << 4) + +#define CS1_CFG_MASK 0x0000000c +#define CS1_CFG_DISABLE 0x00000000 +#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004 +#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008 +#define CS1_CFG(i) ((i) << 2) + +#define CS0_CFG_MASK 0x00000003 +#define CS0_CFG_DISABLE 0x00000000 +#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001 +#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002 +#define CS0_CFG(i) ((i) << 0) + +#endif