Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58172 )
Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices ......................................................................
mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7.
The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
TEST: - Boot into system software
Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 2 files changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc index 9cb0f1d..2903dd1 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += mainboard.c
SPD_SOURCES = mc_ehl2 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c new file mode 100644 index 0000000..4ae857c --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +void variant_mainboard_final(void) +{ + /* PIR8 register mapping for PCIe root ports + INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ + pcr_write16(PID_ITSS, 0x3150, 0x1032); +}