[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function

[Subrata Banik (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 )

Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55225/comment/a2f3e829_8c1b8e63 
PS1, Line 12: This would help to increase the code readability and in future
            : meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly
> Me too! […]

Thanks Furquan and Tim for your support as always.

Coming to Tim's proposal, yes, its a valid request. I have started working with FSP team to see if we can club those meaning UPDs inside a structure