[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email )

Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/84103/comment/8149abbb_60e31ec5?usp... :
PS3, Line 110: SOC_INTEL_COMMON_BLOCK_ACPI_GPE1
> suggestion, looks like we don't need a CPP if we follow the below method […]

Hi Subrata,

I've looked into this approach of using GPE1_STS as conditional flag. GPE1_STS/EN will need to be added for the existing SOC headers. And these headers are SOC pm.h,
where GPE0_STS/_EN() are defined. But, this header is not included in the ASL files. Currently, we only include SOC gpe.h. In the ASL, we were to use this new _GPE1 kconfig to determine the _Lxx events and add the event methods accordingly.
In addition, the same Kconfig is to be used to determine whether GPE0 or GPE1 event bit is used in the devicetree. For instance:

device ref cnvi_wifi on
    		chip drivers/wifi/generic
    			register "wake" = "CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) ? GPE1_CNVI_PME_B0 : GPE0_PME_B0"
    			device generic 0 on end
    		end
    	end

Also, even with GPE1 support, we might want o switch back to merely use the aggregated GPE0 STD events if any of fine GPE1 bit event not working or for debug purpose. The Kconfig might be preferred in this case.

Should we add these two patches as part of our PTL upstream CLs so that I can add the corresponding SOC and MB GPE1 CLs for the complete view of this intension? or I can also include the related changed files in the cros bug 362310295? Please let me know.