Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84699?usp=email )
Change subject: mb/google/rauru: Pre-initialize PCIe at the bootblock stage ......................................................................
mb/google/rauru: Pre-initialize PCIe at the bootblock stage
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. Right now we simply wait for 100ms in ramstage for that.
To speed up the boot time, pre-initialize PCIe by asserting PERST# earlier in the bootblock stage. The pre-initialization time is stored in the early init data region, so that the PCIe initialization in ramstage could make sure the required 100ms delay is still reached. This pre-initialization will speed up the boot time by 100ms on rauru.
TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620
Signed-off-by: Jianjun Wang jianjun.wang@mediatek.com Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/mainboard/google/rauru/bootblock.c 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index b1f9863..e0717aa 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,7 @@
#include <bootblock_common.h> #include <gpio.h> +#include <soc/pcie.h> #include <soc/spi.h>
#include "gpio.h" @@ -13,6 +14,9 @@
void bootblock_mainboard_init(void) { + if (CONFIG(PCI)) + mtk_pcie_pre_init(); + mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios();