[coreboot-gerrit] Change in coreboot[master]: drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )

Change subject: drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems
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Patch Set 19: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/43741/18/src/drivers/spi/tpm/tpm.c 
File src/drivers/spi/tpm/tpm.c:

https://review.coreboot.org/c/coreboot/+/43741/18/src/drivers/spi/tpm/tpm.c@... 
PS18, Line 485: CONFIG_TPM_BOARD_CFG
> Bummer, it should have been CR50_BOARD_CFG_VALUE, which is now computed based on Kconfig setting CR5 […]

You can run

util/abuild/abuilt -t GOOGLE_VOLTEER -c max -x

from the upstream coreboot checkout to build a board. You may need run

make crossgcc

once to build the compiler, but then it will stick around even if you check out different commits.