[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add report_platform.c

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20068

Change subject: soc/intel/cannonlake: Add report_platform.c
......................................................................

soc/intel/cannonlake: Add report_platform.c

Dump basic platform information early in bootblock.

Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef
Signed-off-by: Andrey Petrov 
---
A src/soc/intel/cannonlake/bootblock/report_platform.c
1 file changed, 151 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/20068/1

diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
new file mode 100644
index 0000000..5c4c0eb
--- /dev/null
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/pci.h>
+#include <soc/bootblock.h>
+#include <soc/cpu.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
+#include <string.h>
+
+static struct {
+	u32 cpuid;
+	const char *name;
+} cpu_table[] = {
+	{ CPUID_CANNONLAKE_A0, "Cannonlake A0" },
+	{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
+	{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
+};
+
+static struct {
+	u16 mchid;
+	const char *name;
+} mch_table[] = {
+	{ MCH_CANNONLAKE_ID_U, "Cannonlake-U" },
+	{ MCH_CANNONLAKE_ID_Y, "Cannonlake-Y" },
+};
+
+static struct {
+	u16 igdid;
+	const char *name;
+} igd_table[] = {
+	{ IGD_CANNONLAKE_GT2_SULXM, "Cannonlake ULX GT2" },
+	{ IGD_CANNONLAKE_GT2_SULTM, "Cannonlake ULT GT2" },
+	{ IGD_CANNONLAKE_GT2_SULT_1M, "Cannonlake ULT GT2" },
+	{ IGD_CANNONLAKE_GT2_SULT_2M, "Cannonlake ULT GT2" },
+	{ IGD_CANNONLAKE_GT2_SULT_3M, "Cannonlake ULT GT2" },
+	{ IGD_CANNONLAKE_GT2_SULT_4M, "Cannonlake ULT GT2" },
+};
+
+static void report_cpu_info(void)
+{
+	struct cpuid_result cpuidr;
+	u32 i, index;
+	char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
+	int vt, txt, aes;
+	msr_t microcode_ver;
+	static const char * const mode[] = {"NOT ", ""};
+	const char *cpu_type = "Unknown";
+
+	index = 0x80000000;
+	cpuidr = cpuid(index);
+	if (cpuidr.eax < 0x80000004) {
+		strcpy(cpu_string, "Platform info not available");
+	} else {
+		u32 *p = (u32 *) cpu_string;
+		for (i = 2; i <= 4; i++) {
+			cpuidr = cpuid(index + i);
+			*p++ = cpuidr.eax;
+			*p++ = cpuidr.ebx;
+			*p++ = cpuidr.ecx;
+			*p++ = cpuidr.edx;
+		}
+	}
+	/* Skip leading spaces in CPU name string */
+	while (cpu_name[0] == ' ')
+		cpu_name++;
+
+	microcode_ver.lo = 0;
+	microcode_ver.hi = 0;
+	wrmsr(0x8B, microcode_ver);
+	cpuidr = cpuid(1);
+	microcode_ver = rdmsr(0x8b);
+
+	/* Look for string to match the name */
+	for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+		if (cpu_table[i].cpuid == cpuidr.eax) {
+			cpu_type = cpu_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+	       cpuidr.eax, cpu_type, microcode_ver.hi);
+
+	aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+	txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+	vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+	printk(BIOS_DEBUG,
+		"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+		mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+	int i;
+	u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
+	u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+	const char *mch_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+		if (mch_table[i].mchid == mchid) {
+			mch_type = mch_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+	       mchid, mch_revision, mch_type);
+}
+
+static void report_igd_info(void)
+{
+	int i;
+	u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
+	const char *igd_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+		if (igd_table[i].igdid == igdid) {
+			igd_type = igd_table[i].name;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+	       igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);
+}
+
+void report_platform_info(void)
+{
+	report_cpu_info();
+	report_mch_info();
+	report_igd_info();
+}