Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c File src/soc/rockchip/rk3399/clock.c:
Line 373: PLL_FRAC_MODE << PLL_DSMPD_SHIFT));
I believe this fractional mode is different with the pll fractional divider
In other word, the SSC register just enable the decimal mode, do not set the fractional frequency, the clock is calculated in different ways.