Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52628 )
Change subject: soc/intel/cannonlake: Clean up root port structs ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/cannonlake/chip.c:
https://review.coreboot.org/c/coreboot/+/52628/comment/1ed19945_ab111c5b PS2, Line 19: static const struct pcie_rp_group pch_rp_groups[] = { : #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, : #else : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : #endif : { 0 } : }; : what about this, like on the parent?
static const struct pcie_rp_group pch_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, #endif { 0 } };