[coreboot-gerrit] Change in coreboot[master]: drivers/spi/tpm: Add helper to identify how cr50 sees AP reset

[Karthik Ramasubramanian (Code Review)]

Hello Karthikeyan Ramasubramanian,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44653

to review the following change.

Change subject: drivers/spi/tpm: Add helper to identify how cr50 sees AP reset
......................................................................

drivers/spi/tpm: Add helper to identify how cr50 sees AP reset

Introduce a helper to identify if Cr50 uses SYS_RESET# signal to
observer the AP reset. This helper is used to trigger an appropriate AP
reset when CSE Lite jumps from RO to RW.

BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is
triggered when cr50 is running firmware versions newer than 0.0.22. On
cr50 versions 0.0.22 or older, EC triggers cold reset of AP.

Change-Id: Id84b152993f253878a6c133cc433a0da2c990cf2
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/drivers/spi/tpm/tpm.c
M src/drivers/spi/tpm/tpm.h
2 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44653/1

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index bc40e852..64969cb 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -849,3 +849,16 @@

return payload_size;
 }
+
+bool cr50_sees_ap_reset_on_sys_reset(void)
+{
+	/* Cr50 observes AP Reset using SYS_RESET# signal on or before version 0.0.22 */
+	if (cr50_firmware_version.epoch == 0 && cr50_firmware_version.major == 0 &&
+	    cr50_firmware_version.minor <= 22)
+		return true;
+
+	printk(BIOS_INFO, "Cr50 firmware does not use SYS_RESET#, version: %d.%d.%d\n",
+	       cr50_firmware_version.epoch, cr50_firmware_version.major,
+	       cr50_firmware_version.minor);
+	return false;
+}
diff --git a/src/drivers/spi/tpm/tpm.h b/src/drivers/spi/tpm/tpm.h
index b3e3f45..eb15160 100644
--- a/src/drivers/spi/tpm/tpm.h
+++ b/src/drivers/spi/tpm/tpm.h
@@ -44,4 +44,7 @@
 /* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */
 bool cr50_is_long_interrupt_pulse_enabled(void);

+/* Indicates whether Cr50 observes AP reset using SYS_RESET# signal. */
+bool cr50_sees_ap_reset_on_sys_reset(void);
+
 #endif  /* ! __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H */