[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 70:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpio_defs.h:

https://review.coreboot.org/c/coreboot/+/83789/comment/d628d83a_5cf21c5c?usp... :
PS49, Line 260: GPP_E_OFFSET
> > Subrata, I just contacted our EDS owner and was told that GPP_E0 is a no connect pin (not bonded o […]

True. However, the GPP_E00 offset 0x9a0 is used for GPP_E group starting address in the GPIO ASL file and total number of GPP_E group pin is 25, E00-E22 + two internal used PADs at the end as defined in SOC gpio_soc_defs.h. We just treat it as internal only PAD and don't use it.