Attention is currently required from: Bora Guvendik, Elyes Haouas, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik.
Cliff Huang has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 82:
(2 comments)
Patchset:
PS82:
Please also confirm the address. […]
I just check FAP, there is no DMI. We can add DMI_BASE_SIZE = 0 in iomap.h. and add #if condition in soc/intel/common/block/acpi/acpi/northbridge.asl in separate CL:
#if DMI_BASE_SIZE
/* DMI BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.68h
*/
Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB)
#endif
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/75530cbd_2021b814?usp... :
PS82, Line 54: config SOC_INTEL_PANTHERLAKE_H
Can we add SOC_INTEL_PANTHERLAKE_U? Currently, we have […]
Sure. Let me also check with EDS owner for UFS section. In the mean time, let's remove ufs.asl for now.
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