[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/rex: Skip UART0 config in FSP

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83750?usp=email )

Change subject: mb/google/rex: Skip UART0 config in FSP
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mb/google/rex: Skip UART0 config in FSP

UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.

Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/83750/1

diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 1a80e2a..00acbec 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -73,7 +73,7 @@
    register "skip_ext_gfx_scan" = "1"

register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
    	[PchSerialIoIndexUART1] = PchSerialIoDisabled,
    	[PchSerialIoIndexUART2] = PchSerialIoDisabled,
    }"