[coreboot-gerrit] [M] Change in coreboot[master]: mb/siemens/mc_apl2: Enable early POST through NC_FPGA

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68743 )

Change subject: mb/siemens/mc_apl2: Enable early POST through NC_FPGA
......................................................................

mb/siemens/mc_apl2: Enable early POST through NC_FPGA

Enable early POST code output for this mainboard, using
the NC FPGA device on PCIe.

This requires the parent PCI bridge to be initialized early.

BUG=none
TEST=boot on siemens/mc_apl2 and observe whether the POST
codes coming from before FSP-M init are visible

Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a
Signed-off-by: Jan Samek 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743
Tested-by: build bot (Jenkins) 
Reviewed-by: Uwe Poeche 
Reviewed-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc
A src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c
3 files changed, 51 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
  Uwe Poeche: Looks good to me, but someone else must approve

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig
index 933e594..99ebc6e 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig
@@ -7,6 +7,7 @@
    select DRIVERS_I2C_RX6110SA
    select RX6110SA_DISABLE_ACPI
    select DRIVER_SIEMENS_NC_FPGA
+	select NC_FPGA_POST_CODE
    select MAINBOARD_HAS_TPM2
    select MEMORY_MAPPED_TPM
    select TPM_ON_FAST_SPI
@@ -27,4 +28,19 @@
 config FMDFILE
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd"

+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x13
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
 endif # BOARD_SIEMENS_MC_APL2
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc
index 152b46e..9ec2c80 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc
@@ -2,3 +2,5 @@

ramstage-y += gpio.c
 ramstage-y += mainboard.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c
new file mode 100644
index 0000000..c34e253
--- /dev/null
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}