Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37872 )
Change subject: biostar/a68n_5200: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/a68n_5200: Switch away from ROMCC_BOOTBLOCK
Following the examples of change CB:37737 (ee8f969) and CB:37829. Warning: Not tested on hardware, please test if you have this board.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37 --- M src/mainboard/biostar/a68n_5200/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig.name M src/mainboard/biostar/a68n_5200/Makefile.inc A src/mainboard/biostar/a68n_5200/bootblock.c D src/mainboard/biostar/a68n_5200/romstage.c 5 files changed, 56 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37872/1
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index f608513..e4271d3 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -15,14 +15,10 @@ # GNU General Public License for more details. #
-config BOARD_BIOSTAR_A68N5200 - def_bool n - if BOARD_BIOSTAR_A68N5200
config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name index 6d765d2..52a7f15 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig.name +++ b/src/mainboard/biostar/a68n_5200/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_BIOSTAR_A68N5200 -# bool"A68N-5200" +config BOARD_BIOSTAR_A68N5200 + bool "A68N-5200" diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/biostar/a68n_5200/Makefile.inc +++ b/src/mainboard/biostar/a68n_5200/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/biostar/a68n_5200/bootblock.c b/src/mainboard/biostar/a68n_5200/bootblock.c new file mode 100644 index 0000000..3d36956 --- /dev/null +++ b/src/mainboard/biostar/a68n_5200/bootblock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <southbridge/amd/common/amd_defs.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +static void sbxxx_enable_48mhzout(void) +{ + u32 reg32; + + /* most likely programming to 48MHz out signal */ + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xfff8ffff; + SB_MMIO_MISC32(0x28) = reg32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= 0xffffbffb; + SB_MMIO_MISC32(0x40) = reg32; +} + +void bootblock_mainboard_early_init(void) +{ + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Enable serial output on it8728f */ + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c deleted file mode 100644 index 5d210fa..0000000 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Edward O'Callaghan funfunctor@folklore1984.net - * Copyright (C) 2017 Damien Zammit damien@zamaudio.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SB_MMIO 0xFED80000 -#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) - -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); - reg32 &= 0xfff8ffff; - SB_MMIO_MISC32(0x28) = reg32; - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = SB_MMIO_MISC32(0x40); - reg32 &= 0xffffbffb; - SB_MMIO_MISC32(0x40) = reg32; -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u8 byte; - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* enable SIO LPC decode */ - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* run ite */ - sbxxx_enable_48mhzout(); - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -}