[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )

Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... 
PS3, Line 123: TcssD3ColdEnable
> Typically soc_intel_tigerlake_config elements are aligned with fsp upd. […]

I mean we need to remove all TcssD3ColdEnable across both of Volteer and TGLRVP first. Then update this patch.