[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Werner Zeh, Felix Held.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 57:

(1 comment)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/a0735cb5_358e0d68 
PS52, Line 129: /* Set the ownership of these devices to PSE */
              : 		params->PchPseDmaEnable[0] = PSE_Owned;
              : 		params->PchPseUartEnable[2] = PSE_Owned;
              : 		params->PchPseHsuartEnable[2] = PSE_Owned;
              : 		params->PchPseI2cEnable[2] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[0] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[1] = PSE_Owned;
              : 		/* Disable PSE DMA Sideband Interrupt for DMA 0 */
              : 		params->PchPseDmaSbInterruptEnable[0] = 0;
              : 		/* Set the log output to PSE UART 2 */
              : 		params->PchPseLogOutputChannel = 3;
> Yes, both alternatives are fine with me.

Thanks Paul again. Done added the comments. Please help to check.