Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6499
-gerrit
commit c3ab7c8d471ef08d7ce943052573e2005c2ee38a Author: Dave Frodin dave.frodin@se-eng.com Date: Tue Aug 5 10:20:59 2014 -0600
gizmosphere/gizmo: Change the PCIe GPP to two x1 ports
Gizmo sends two southbridge GPP PCIe lanes to its high speed edge connector. This change will allow developers to create two x1 slots on an extender card.
Change-Id: Iba6c1a4caf7846d12e3960775d7bc906ca8ff385 Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/mainboard/gizmosphere/gizmo/devicetree.cb | 5 +++-- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 301f79a..8cd4cd3 100755 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -50,10 +50,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.3 on end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed device pci 14.5 off end # USB 2 - device pci 15.0 on end # PCIe PortA # PCIe x4 slot off of high speed edge connector + device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector + device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector device pci 16.0 off end # OHCI USB3 device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 device pci 18.0 on end diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 0c9fa86..401d981 100755 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -185,7 +185,7 @@ * GPP_CFGMODE_X2110 * GPP_CFGMODE_X1111 */ -#define GPP_CFGMODE GPP_CFGMODE_X4000 +#define GPP_CFGMODE GPP_CFGMODE_X1111
/** * @def NB_SB_GEN2