[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add support for FSP CNVi pin muxing

[Furquan Shaikh (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, Boris Mittelberg.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51110 )

Change subject: soc/intel/alderlake: Add support for FSP CNVi pin muxing
......................................................................

Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51110/comment/b38b202a_c94f1606 
PS1, Line 8: 
Based on the comment on CB:51111, I am guessing this CL is also not required anymore.