Attention is currently required from: Paul Menzel. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 )
Change subject: mb/acer/g43t-am3: Add documentation ......................................................................
Patch Set 2:
(7 comments)
Patchset:
PS2: Thank you for having a look. I wrapped the lines to something below 79, I hope that is what you intended.
Good point about the board status, I think I can update it this weekend.
File Documentation/mainboard/acer/g43t-am3.md:
https://review.coreboot.org/c/coreboot/+/56838/comment/40e4f9cb_23ed8f62 PS1, Line 25: There is no serial port. Serial console output is possible by soldering to a point at the corresponding Super I/O pin and patching the mainboard-specific code accordingly.
Please wrap the line.
Done
https://review.coreboot.org/c/coreboot/+/56838/comment/b761babe_98980e68 PS1, Line 30:
Please mention the payload and OS version.
Done. Should I add a note how to boot Windows 10? It needs the VGA BIOS and libgfxinit disabled. I want to test libgfxinit linear framebuffer + TianoCore, but I would have to reduce ME size to fit TianoCore, still on my list.
https://review.coreboot.org/c/coreboot/+/56838/comment/4b373504_b893401c PS1, Line 41: + PS/2 mouse and keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500)
For SeaBIOS payload. […]
Yes there it works. I didn't know how to boot from USB with FILO so that's all I can say about that payload.
I added these notes in two indented list items, is that okay?
https://review.coreboot.org/c/coreboot/+/56838/comment/1a4033ad_a4105355 PS1, Line 49: + DDR3 memory with 512Mx8 chips (G43 limitation)
So it does not work with the vendor firmware either, right?
I don't have that particular RAM at hand anymore but I'm pretty sure it doesn't. My 4GB sticks with sixteen 256Mx8 chips already make it fail (it beeps continuously once powered on).
Maybe leave it out if it is a chipset limitation, which I think it is without having any good reference?
https://review.coreboot.org/c/coreboot/+/56838/comment/ae8e9aec_91539721 PS1, Line 110: ``` : +---+---+ : SPI_CSn <- | x | x | -> VCC : +---+---+ : SPI_MISO <- | x | x | -> HOLDn : +---+---+ : WPn <- | x | x | -> SPI_CLK : +---+---+ : GND <- | x | x | -> SPI_MOSI : +---+---+ : ```
I’d just indent it by four spaces to mark it up as code block.
Done
https://review.coreboot.org/c/coreboot/+/56838/comment/cdabe639_88d72f6b PS1, Line 129: During a discussion in #coreboot on IRC, ECS was suspected to be the original designer of this series of mainboards. They have similar models such as the ECS G43T-WM.
Though not important for the rendered output, please continue the line above.
Done