Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63500 )
Change subject: soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S ......................................................................
soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc 2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63500/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2eeae42..9162cd9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -98,11 +98,11 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_TCSS if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC - select SOC_INTEL_COMMON_BLOCK_USB4 - select SOC_INTEL_COMMON_BLOCK_USB4_PCIE - select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_USB4 if !SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE if !SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 825cfd5..e3564aa 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -37,7 +37,7 @@ ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c -ramstage-y += retimer.c +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_RETIMER) += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += tcss.c