EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48111 )
Change subject: mb/google/brya: Enable building for Chrome OS ......................................................................
mb/google/brya: Enable building for Chrome OS
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/variants/baseboard/gpio.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 6 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/48111/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 4348ef5..1d29f90 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -3,6 +3,7 @@ select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_ALDERLAKE
if BOARD_GOOGLE_BASEBOARD_BRYA @@ -11,6 +12,11 @@ def_bool n select SYSTEM_TYPE_LAPTOP
+config CHROMEOS + bool + default y + select VBOOT_LID_SWITCH + config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index cdd0eb6..3735e20 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -1,7 +1,12 @@ bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c new file mode 100644 index 0000000..e222ca2 --- /dev/null +++ b/src/mainboard/google/brya/chromeos.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} + diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index f15f25e..5930430 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -26,4 +26,7 @@ } /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> } diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 0f5b298..8179e2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { @@ -25,3 +26,12 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 8531f7d..6e31712 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -10,5 +10,6 @@ * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num);
#endif /*__BASEBOARD_VARIANTS_H__ */