[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Correct read width in RMW cycle

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47098 )

Change subject: sb/intel/lynxpoint: Correct read width in RMW cycle
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Patch Set 4:

(1 comment)

File src/southbridge/intel/lynxpoint/sata.c:

https://review.coreboot.org/c/coreboot/+/47098/comment/554b751d_c22cfedd 
PS4, Line 70: 	reg32 = pci_read_config32(dev, 0x98);
> This was likely done on purpose to not clear bits [16:32]. […]

IIRC, I checked reference code and it does a 32-bit read. I'll check again and update the commit message accordingly (say "reference code version F.O.O does this" or similar).

Until then, I'm leaving this as unresolved