Hello Naresh Solanki, Kyösti Mälkki, Patrick Rudolph, Hung-Te Lin, Subrata Banik, Tristan Corrick, Maxim Polyakov, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35880
to look at the new patch set (#5).
Change subject: [RFC] src/soc/intel: FSP2.0 platforms: FSP param CdClock ......................................................................
[RFC] src/soc/intel: FSP2.0 platforms: FSP param CdClock
This is not for review but is kept for discussion. Some of the changes of this CB have been split off to CB:36348 and following.
Currently CdClock is set per-board (asrock/h110m, intel/kblrvp) or kept as set in the FSP binary defaults. According to Intel's Open Source Graphics PRM [1] it must be set SoC-dependent.
I see two options: a) make CdClock (and probably GtFreqMax, too) a mainboard-specific devicetree setting. b) set it, like VR config is done, depending on the detected SoC
[1] https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-disp...
Change-Id: Ie3bd7f3dc4c795691a04d2eaba0e2458ee50aabb Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/asrock/h110m/ramstage.c M src/mainboard/intel/kblrvp/ramstage.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip_fsp20.c 5 files changed, 19 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35880/5