Attention is currently required from: Jason Glenesk, Paul Menzel, Fred Reitberger.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69705 )
Change subject: mb/amd/birman: Update DXIO descriptors per schematic
......................................................................
Patch Set 17:
(2 comments)
File src/mainboard/amd/birman/port_descriptors_phoenix.c:
https://review.coreboot.org/c/coreboot/+/69705/comment/59df6fe9_a29ad962
PS16, Line 113: .start_logical_lane = 15, \
: .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \
can the start lane be greater than the end lane? might be a good idea to try if the dxio logic will dislike this or check with the reference code
File src/mainboard/amd/birman/port_descriptors_phoenix.c:
https://review.coreboot.org/c/coreboot/+/69705/comment/2bd6a83b_5f61ab06
PS17, Line 65: CLK_REQ4
CLK_REQ1?
--
To view, visit
https://review.coreboot.org/c/coreboot/+/69705
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
Gerrit-Change-Number: 69705
Gerrit-PatchSet: 17
Gerrit-Owner: Fred Reitberger
reitbergerfred@gmail.com
Gerrit-Reviewer: Felix Held
felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@mailbox.org
Gerrit-CC: ritul guru
ritul.bits@gmail.com
Gerrit-Attention: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Attention: Paul Menzel
paulepanter@mailbox.org
Gerrit-Attention: Fred Reitberger
reitbergerfred@gmail.com
Gerrit-Comment-Date: Tue, 18 Apr 2023 22:08:54 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment