Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31445 )
Change subject: soc/intel/cannonlake: Add a power control workaround for SD controller ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
I agree to the ASL code beside my inline question. Two remarks, though:
Why is it a workaround? Is it documented somewhere that it should behave differently?
Why the additional Kconfig? Can't we simply read the pad mode in _PS3 and do what needs to be done if it was set to native1?
https://review.coreboot.org/#/c/31445/2/src/soc/intel/cannonlake/acpi/scs.as... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/#/c/31445/2/src/soc/intel/cannonlake/acpi/scs.as... PS2, Line 134: CTXS(SD_PWR_EN_PIN) What about other bits like enabling the output buffer? Are they all guaranteed to have the correct value?