Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32017
Change subject: mb/google/hatch: Enable FP MCU ......................................................................
mb/google/hatch: Enable FP MCU
AP communicates with FP MCU through gspi1.
BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen shchen@google.com
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32017/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0299ded..28cc888 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| GSPI1 | FP MCU | #| I2C0 | Touchpad | #| I2C1 | Touch screen | #| I2C4 | Audio | @@ -34,6 +35,10 @@ .speed_mhz = 1, .early_init = 1, }, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -290,7 +295,17 @@ device spi 0 on end end end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" # GPP_A23 + device spi 1 on end + end # FPMCU + end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end