[coreboot-gerrit] Change in coreboot[master]: vendorcode/mt8192: limit fast-k frequency count from 7 to 3

[Xi Chen (Code Review)]

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51406 )

Change subject: vendorcode/mt8192: limit fast-k frequency count from 7 to 3
......................................................................

vendorcode/mt8192: limit fast-k frequency count from 7 to 3

For bootup faster.

Signed-off-by: Xi Chen 
Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d
---
M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
1 file changed, 21 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/51406/1

diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
index d0e16d4..1134559 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
@@ -12,6 +12,7 @@
 #include "dramc_pi_api.h"
 #include <soc/dramc_param.h>
 #include <soc/emi.h>
+#include <types.h>

DRAMC_CTX_T dram_ctx_chb;

@@ -1299,6 +1300,7 @@

DRAMC_CTX_T * p;
    U8 final_shu;
+	DRAM_DFS_FREQUENCY_TABLE_T *first_cali_freq_tbl;

#ifdef DDR_INIT_TIME_PROFILING
    U32 CPU_Cycle;
@@ -1403,11 +1405,12 @@

// DramC & PHY init for all channels
    //===  First frequency ======
+	first_cali_freq_tbl = &gFreqTbl[DRAM_DFS_SHUFFLE_MAX-1];

#if defined(DUMP_INIT_RG_LOG_TO_DE)
    vSetDFSFreqSelByTable(p, &gFreqTbl[1]); //0:3200 1:4266, 2:800, 3:1866, 4:1200, 5:2400, 6:1600
 #else
-	vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SHUFFLE_MAX-1]);
+	vSetDFSFreqSelByTable(p, first_cali_freq_tbl);
    //vSetDFSFreqSelByTable(p, &gFreqTbl[1]);
 #endif
    //#if (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF) || defined(FIRST_BRING_UP) || (__FLASH_TOOL_DA__)
@@ -1509,6 +1512,16 @@
    #endif

S8 u1ShuIdx;
+	S8 allCaliShuIdx = 0xFF;
+
+	if (CONFIG(MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT)) {
+		if (p->DRAMPinmux == PINMUX_DSC)
+			allCaliShuIdx = 0x61;	// 3200, 2400, 1600
+		else
+			allCaliShuIdx = 0x43;	// 3200, 4266, 1600
+	}
+	dramc_debug("all cali shu idx: 0x%x\n", allCaliShuIdx);
+
 //#if (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF)
    if (is_dvfs_enabled()) {
    	for (u1ShuIdx = DRAM_DFS_SHUFFLE_MAX - 2; u1ShuIdx >= DRAM_DFS_SHUFFLE_1; u1ShuIdx--)
@@ -1518,6 +1531,13 @@
    			continue;
    		#endif

+			// ignore the calibration for shuffle which is not in allCaliShuIdx, just copy first cali shuffle data
+			if (!(allCaliShuIdx & BIT(u1ShuIdx))) {
+				// copy first calibration shuffle to this shuffle (if DVFS, need double confirm)
+				DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx);
+				continue;
+			}
+
    		vSetDFSFreqSelByTable(p, &gFreqTbl[u1ShuIdx]);
    		#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
    		DramcSave_Time_For_Cal_Init(p);