[coreboot-gerrit] [M] Change in coreboot[master]: vendorcode/amd/fsp/common: Refactor dmi_info.h

[Martin L Roth (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Konrad Adamczyk, Matt DeVillier, Raul Rangel.

Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email )

Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h
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Patch Set 2:

(5 comments)

Patchset:

PS2: 
I think we should list what's actually supported by coreboot, not the theoretical maximums supported by the silicon.  These are limited by the packages we support to far below what the the limits in AGESA are set to, which seems ridiculously high.

File src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h:

https://review.coreboot.org/c/coreboot/+/76107/comment/74096437_68b3b09b :
PS2, Line 9: 
coreboot only supports FP6 for Cezanne

FP6 Motherboard Design guide: #56178E Rev .50
1 socket, 2 channels, 1 dimms per channel.

If am5 socket support gets added, we can update it to 2 dimms per channel at that point.

1/2/1

File src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h:

https://review.coreboot.org/c/coreboot/+/76107/comment/15c22baf_d7cfc944 :
PS2, Line 10: #define MAX_SOCKETS_SUPPORTED     2   ///< Max number of sockets in system
            : #define MAX_CHANNELS_PER_SOCKET   8   ///< Max Channels per sockets
            : #define MAX_DIMMS_PER_CHANNEL     4   ///< Max DIMMs on a memory channel (independent of platform)
            :
> I *think* mendocino is 4/12/2 here like phoenix - at least that matches the constants in the FSP cod […]

MDN is only available on FT6 and only supports 2 LPDDR 'DIMMS'

I think this should be 1/2/1

File src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h:

https://review.coreboot.org/c/coreboot/+/76107/comment/0b43b97c_9c76a367 :
PS2, Line 10: #define MAX_SOCKETS_SUPPORTED     4   ///< Max number of sockets in system
            : #define MAX_CHANNELS_PER_SOCKET   12  ///< Max Channels per sockets
            : #define MAX_DIMMS_PER_CHANNEL     2   ///< Max DIMMs on a memory channel (independent of platform)
MB Design guide for FP7/FP7R2: #56920 Rev1.06
FP7/FP7R2 supports 1 socket, 2 channels, 1 dimm per channel

MB Design guide for FP8: #57263 Rev .92
FP8 supports 1 socket, 4 32-bit channels LPDDR5/5x, 1 dimm per channel.

This is somewhat confusing though as each "DIMM" will have 2 32-bit channels.  As far as SMBIOS is concerned, I think this should be reported as 1/2/1, but AGESA may report 1/4/1, so who knows.

1/2/1 ?

File src/vendorcode/amd/fsp/picasso/soc_dmi_info.h:

https://review.coreboot.org/c/coreboot/+/76107/comment/f5c52b81_55003785 :
PS2, Line 9: 
Picasso is only on FP5 socket.

FP5 Motherboard design guide: #55597 Rev 1.18
FP5 supports 1 socket, 2 channels, 1 dimm per channel

1/2/1