Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 )
Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/voltee... PS3, Line 136: BIT(2)
I think we could make a nice set of #define for this, here's my suggestion: […]
Done
https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/voltee... PS3, Line 129: /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= BIT(2); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : }
I think this should go in fw_config.c as well. […]
hmmm... can we update struct soc_intel_tigerlake_config from there? i think this needs to happen when called from platform_fsp_silicon_init_params_cb().
https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/voltee... PS3, Line 34: #define TGL_GPIO_ID_GPP_E22 0x090E0016 : #define TGL_GPIO_ID_GPP_E23 0x090E0017 :
I think we can do a little better here too 😊 […]
that's a question for brandon.breitenstein@intel.com. i'm not introducing new values here, all of this is based on what we already have in the device trees.